Abstract

A lateral polysilicon Bipolar Charge Plasma Transistor (poly-Si BCPT) on undoped recrystallized polycrystalline silicon which is compatible with the thin-film field effect transistor (TFT) fabrication is reported in this paper. Using calibrated two-dimensional device simulation, the electrical performance of the poly-Si BCPT is evaluated in detail by considering the position of the single grain boundary. Our simulation results demonstrate that the poly-Si BCPT has the potential to realize low-cost thin-film polycrystalline silicon bipolar transistors with large current gain and cut-off frequency making it suitable for a number of applications including the driver circuits of the displays.

© 2014 IEEE

PDF Article

References

  • View by:
  • |
  • |

  1. T. Tanaka, H. Asuma, K. Ogawa, Y. Shinagawa, N. Konishi, "An LCD addressed by a-Si:H TFTs with peripheral poly-Si TFT circuits," IEDM Tech. Dig. (1993) pp. 389-392.
  2. T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanaka, N. Hashimoto, A. Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda, T. Nagano, "Advanced TFT SRAM cell technology using a phase-shift lithography," IEEE Trans. Electron Devices 42, 1305-1313 (1995).
  3. G. Fortunato, A. Pecora, L. Maiolo, "Poly-silicon thin-film transistors on polymer substrates," J. Mater. Science in Semicond. Process. 15, 627-641 (2012).
  4. M. Kimura, I. Yudasaka, S. Kanbe, H. Kobayashi, H. Kiguchi, S. Seki, S. Miyashita, T. Shimoda, T. Ozawa, K. Kitawada, T. Nakazawa, W. Miyazawa, H. Ohshima, "Low-temperature polysilicon thin-film transistor driving with integrated driver for high-resolution light emitting polymer display," IEEE Trans. Electron Devices 46, 2282-2288 (1999).
  5. S. Y. Kim, W. F. Loke, S. P. Park, B. Jung, K. Roy, "Poly-Si thin film transistors: Opportunities for low-cost RF applications," IEEE Intern. Conf. IC Design & Technology (ICICDT) (2012) pp. 1-4.
  6. T. Tsai, K. M. Chen, H. C. Lin, T. Y. Lin, C. J. Su, T. S. Chao, T. Y. Huang, "Low-operating-voltage ultrathin junctionless poly-Si thin-film transistor technology for RF applications," IEEE Electron Device Lett. 33, 1565-1567 (2012).
  7. K. Banerjee, S. J. Souri, P. Kapur, K. C. Saraswat, "3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proc. IEEE 89, 602-633 (2001).
  8. A. J. Walker, "Sub-50-nm dual-gate thin-film transistors for monolithic 3-D flash," IEEE Trans. Electron Devices 56, 2703-2710 (2009).
  9. P. M. Walker, H. Mizuta, S. Uno, Y. Furuta, D. G. Hasko, "Improved off-current and subthreshold slope in aggressively scaled poly-Si TFTs with a single grain boundary in the channel," IEEE Trans. Electron Devices 51, 212-219 (2004).
  10. G. Kawachi, T. Okada, S. Tsuboi, M. Mitani, "Sub-micron CMOS/MOS-bipolar hybrid TFTs for system displays," IEDM Tech. Dig. (2007) pp. 591-594.
  11. C. Y. Chang, B. S. Wu, Y. K. Fang, R. H. Lee, "Amorphous silicon bipolar transistor with high gain ( $> 12$ ) and high speed ( $> {{30}}~{{ps}}$ )," IEDM Tech. Dig. (1985) pp. 432-435.
  12. J. C. Sturm, J. F. Gibbons, "Vertical bipolar transistors in laser-recrystallized polysilicon," IEEE Electron Device Lett. 6, 400-402 (1985).
  13. B.-Y. Tsaur, D. J. Silversmith, J. C. C. Fan, R. W. Mountain, "Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on ${{SiO}}_{2}$ ," IEEE Electron Device Lett. 4, 269-271 (1983).
  14. T. Mohammad-Brahim, K. Kis-Sion, D. Briand, M. Sarret, O. Bonnaud, J. P. Kleider, C. Longeaud, B. Lambert, "From amorphous to polycrystalline thin films: Dependence on annealing time of structural and electronic properties," J. Non-Cryst. Solids 227–230, 962-966 (1998).
  15. C. A. Dimitriadis, P. A. Coxon, N. A. Economou, "Leakage current of undoped LPCVD polycrystalline silicon thin-film transistors," IEEE Trans. Electron Devices 42, 950-956 (1995).
  16. P. M. Walker, U. Shigeyasu, H. Mizuta, "Simulation study of the dependence of submicron polysilicon thin-film transistor output characteristics on grain boundary position," Jpn. J. Appl. Phys. 44, 8322-8328 (2005).
  17. C.-H. Ho, G. Panagopoulos, K. Roy, "A physical model for grain-boundary-induced threshold voltage variation in polysilicon thin-film transistors," IEEE Trans. Electron Devices 59, 2396-2402 (2012).
  18. J. Li, K. Kang, K. Roy, "Variation estimation and compensation technique in scaled LTPS TFT circuits for low-power low-cost applications," IEEE Trans. Computer-Aided Des. Integr. CircuitsSyst. 28, 46-59 (2009).
  19. S.-Y. Kim, S. Baytok, K. Roy, "Thin-BOX poly-Si thin-film transistors for CMOS-compatible analog operations," IEEE Trans. Electron Devices 58, 1687-1695 (2011).
  20. L. Jing, A. Bansal, K. Roy, "Poly-Si thin-film transistors: An efficient and low-cost option for digital operation," IEEE Trans. Electron Devices 54, 2918-2929 (2007).
  21. S.-Y. Kim, W.-F. Loke, J. Byunghoo, K. Roy, "High-frequency modeling of poly-Si thin-film transistors for low-cost RF applications," IEEE Trans. Electron Devices 59, 2296-2301 (2012).
  22. L. Yiming, J. Y. Huang, B.-S. Lee, C.-H. Hwang, "Effect of single grain boundary position on surrounding-gate polysilicon thin film transistors," 7th IEEE Conf. Nanotechnol. (2007) pp. 1148-1151.
  23. T. C. Liu, J. B. Kuo, "Grain boundary-related kink effects of poly-Si TFTs," IEEE Int. Conf. Electron Devices and Solid State Circuit (EDSSC) (2012) pp. 1-2.
  24. M. J. Kumar, K. Nadda, "Bipolar charge plasma transistor: A novel three terminal device," IEEE Trans. Electron Devices 59, 962-967 (2012).
  25. B. Rajasekharan, R. J. E. Hueting, C. Salm, T. van Hemert, R. A. M. Wolters, J. Schmitz, "Fabrication and characterization of the charge-plasma diode," IEEE Electron Device Lett. 31, 528-530 (2010).
  26. R. J. E. Hueting, B. Rajasekharan, C. Salm, J. Schmitz, "The charge plasma p-n diode," IEEE Electron Device Lett. 29, 1367-1369 (2008).
  27. K. Nadda, M. J. Kumar, "Schottky collector bipolar transistor without impurity doped emitter and base: Design and performance," IEEE Trans. on Electron Devices 60, 2956-2959 (2013).
  28. M. J. Kumar, S. Janardhanan, "Doping-less tunnel field effect transistor: Design and investigation," IEEE Trans. Electron Devices 60, 3285-3290 (2013).
  29. C. A. Dimitriadis, D. H. Tassis, N. A. Economou, A. J. Lowe, "Determination of bulk states and interface states distributions in polycrystalline silicon thin-film transistors," J. Appl. Phys. 74, 2919-2924 (1993).
  30. N. A. Hastas, N. Archontas, C. A. Dimitriadis, G. Kamarinos, T. Nikolaidis, N. Georgoulas, A. Thanailakis, "Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors," Microelectronics Reliability 45, 341-348 (2005).
  31. ATLAS Device Simulation Software Silvaco Int.Santa ClaraCAUSA (2012).
  32. C. Lombardi, S. Manzini, A. Saporito, M. Vanzi, "A physically based mobility model for numerical simulation of nonplanar devices," IEEE Trans. Computer-Aided Des. Integr. Circuits Syst. 7, 1164-1171 (1988).
  33. R. Guerrieri, P. Ciampolini, A. Gnudi, M. Rudan, G. Baccarani, "Numerical simulation of polycrystalline-Silicon MOSFET's," IEEE Trans. Electron Devices 33, 1201-1206 (1986).
  34. S. Selberherr, Analysis and Simulation of Semiconductor Devices (Springer-Verlag, 1984).
  35. K. Yamaguchi, "Modeling and characterization of polycrystalline-silicon thin-film transistors with a channel-length comparable to a grain size," Jpn. J. Appl. Phys. 89, 590-595 (2001).
  36. M. J. Kumar, V. Parihar, "Surface Accumulation Layer Transistor (SALTran): A new bipolar transistor for enhanced current gain and reduced hot-carrier degradation," IEEE Trans. Device Mater. Rel. 4, 509-515 (2004).
  37. M. J. Kumar, P. Singh, "A super beta bipolar transistor using SiGe-base Surface Accumulation Layer Transistor (SALTran) concept: A simulation study," IEEE Trans. Electron Devices 53, 577-579 (2006).

2013 (2)

K. Nadda, M. J. Kumar, "Schottky collector bipolar transistor without impurity doped emitter and base: Design and performance," IEEE Trans. on Electron Devices 60, 2956-2959 (2013).

M. J. Kumar, S. Janardhanan, "Doping-less tunnel field effect transistor: Design and investigation," IEEE Trans. Electron Devices 60, 3285-3290 (2013).

2012 (5)

S.-Y. Kim, W.-F. Loke, J. Byunghoo, K. Roy, "High-frequency modeling of poly-Si thin-film transistors for low-cost RF applications," IEEE Trans. Electron Devices 59, 2296-2301 (2012).

M. J. Kumar, K. Nadda, "Bipolar charge plasma transistor: A novel three terminal device," IEEE Trans. Electron Devices 59, 962-967 (2012).

G. Fortunato, A. Pecora, L. Maiolo, "Poly-silicon thin-film transistors on polymer substrates," J. Mater. Science in Semicond. Process. 15, 627-641 (2012).

T. Tsai, K. M. Chen, H. C. Lin, T. Y. Lin, C. J. Su, T. S. Chao, T. Y. Huang, "Low-operating-voltage ultrathin junctionless poly-Si thin-film transistor technology for RF applications," IEEE Electron Device Lett. 33, 1565-1567 (2012).

C.-H. Ho, G. Panagopoulos, K. Roy, "A physical model for grain-boundary-induced threshold voltage variation in polysilicon thin-film transistors," IEEE Trans. Electron Devices 59, 2396-2402 (2012).

2011 (1)

S.-Y. Kim, S. Baytok, K. Roy, "Thin-BOX poly-Si thin-film transistors for CMOS-compatible analog operations," IEEE Trans. Electron Devices 58, 1687-1695 (2011).

2010 (1)

B. Rajasekharan, R. J. E. Hueting, C. Salm, T. van Hemert, R. A. M. Wolters, J. Schmitz, "Fabrication and characterization of the charge-plasma diode," IEEE Electron Device Lett. 31, 528-530 (2010).

2009 (2)

J. Li, K. Kang, K. Roy, "Variation estimation and compensation technique in scaled LTPS TFT circuits for low-power low-cost applications," IEEE Trans. Computer-Aided Des. Integr. CircuitsSyst. 28, 46-59 (2009).

A. J. Walker, "Sub-50-nm dual-gate thin-film transistors for monolithic 3-D flash," IEEE Trans. Electron Devices 56, 2703-2710 (2009).

2008 (1)

R. J. E. Hueting, B. Rajasekharan, C. Salm, J. Schmitz, "The charge plasma p-n diode," IEEE Electron Device Lett. 29, 1367-1369 (2008).

2007 (1)

L. Jing, A. Bansal, K. Roy, "Poly-Si thin-film transistors: An efficient and low-cost option for digital operation," IEEE Trans. Electron Devices 54, 2918-2929 (2007).

2006 (1)

M. J. Kumar, P. Singh, "A super beta bipolar transistor using SiGe-base Surface Accumulation Layer Transistor (SALTran) concept: A simulation study," IEEE Trans. Electron Devices 53, 577-579 (2006).

2005 (2)

N. A. Hastas, N. Archontas, C. A. Dimitriadis, G. Kamarinos, T. Nikolaidis, N. Georgoulas, A. Thanailakis, "Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors," Microelectronics Reliability 45, 341-348 (2005).

P. M. Walker, U. Shigeyasu, H. Mizuta, "Simulation study of the dependence of submicron polysilicon thin-film transistor output characteristics on grain boundary position," Jpn. J. Appl. Phys. 44, 8322-8328 (2005).

2004 (2)

P. M. Walker, H. Mizuta, S. Uno, Y. Furuta, D. G. Hasko, "Improved off-current and subthreshold slope in aggressively scaled poly-Si TFTs with a single grain boundary in the channel," IEEE Trans. Electron Devices 51, 212-219 (2004).

M. J. Kumar, V. Parihar, "Surface Accumulation Layer Transistor (SALTran): A new bipolar transistor for enhanced current gain and reduced hot-carrier degradation," IEEE Trans. Device Mater. Rel. 4, 509-515 (2004).

2001 (2)

K. Yamaguchi, "Modeling and characterization of polycrystalline-silicon thin-film transistors with a channel-length comparable to a grain size," Jpn. J. Appl. Phys. 89, 590-595 (2001).

K. Banerjee, S. J. Souri, P. Kapur, K. C. Saraswat, "3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proc. IEEE 89, 602-633 (2001).

1999 (1)

M. Kimura, I. Yudasaka, S. Kanbe, H. Kobayashi, H. Kiguchi, S. Seki, S. Miyashita, T. Shimoda, T. Ozawa, K. Kitawada, T. Nakazawa, W. Miyazawa, H. Ohshima, "Low-temperature polysilicon thin-film transistor driving with integrated driver for high-resolution light emitting polymer display," IEEE Trans. Electron Devices 46, 2282-2288 (1999).

1998 (1)

T. Mohammad-Brahim, K. Kis-Sion, D. Briand, M. Sarret, O. Bonnaud, J. P. Kleider, C. Longeaud, B. Lambert, "From amorphous to polycrystalline thin films: Dependence on annealing time of structural and electronic properties," J. Non-Cryst. Solids 227–230, 962-966 (1998).

1995 (2)

C. A. Dimitriadis, P. A. Coxon, N. A. Economou, "Leakage current of undoped LPCVD polycrystalline silicon thin-film transistors," IEEE Trans. Electron Devices 42, 950-956 (1995).

T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanaka, N. Hashimoto, A. Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda, T. Nagano, "Advanced TFT SRAM cell technology using a phase-shift lithography," IEEE Trans. Electron Devices 42, 1305-1313 (1995).

1993 (1)

C. A. Dimitriadis, D. H. Tassis, N. A. Economou, A. J. Lowe, "Determination of bulk states and interface states distributions in polycrystalline silicon thin-film transistors," J. Appl. Phys. 74, 2919-2924 (1993).

1988 (1)

C. Lombardi, S. Manzini, A. Saporito, M. Vanzi, "A physically based mobility model for numerical simulation of nonplanar devices," IEEE Trans. Computer-Aided Des. Integr. Circuits Syst. 7, 1164-1171 (1988).

1986 (1)

R. Guerrieri, P. Ciampolini, A. Gnudi, M. Rudan, G. Baccarani, "Numerical simulation of polycrystalline-Silicon MOSFET's," IEEE Trans. Electron Devices 33, 1201-1206 (1986).

1985 (1)

J. C. Sturm, J. F. Gibbons, "Vertical bipolar transistors in laser-recrystallized polysilicon," IEEE Electron Device Lett. 6, 400-402 (1985).

1983 (1)

B.-Y. Tsaur, D. J. Silversmith, J. C. C. Fan, R. W. Mountain, "Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on ${{SiO}}_{2}$ ," IEEE Electron Device Lett. 4, 269-271 (1983).

IEEE Trans. Computer-Aided Des. Integr. CircuitsSyst. (1)

J. Li, K. Kang, K. Roy, "Variation estimation and compensation technique in scaled LTPS TFT circuits for low-power low-cost applications," IEEE Trans. Computer-Aided Des. Integr. CircuitsSyst. 28, 46-59 (2009).

IEEE Trans. Electron Devices (5)

L. Jing, A. Bansal, K. Roy, "Poly-Si thin-film transistors: An efficient and low-cost option for digital operation," IEEE Trans. Electron Devices 54, 2918-2929 (2007).

S.-Y. Kim, W.-F. Loke, J. Byunghoo, K. Roy, "High-frequency modeling of poly-Si thin-film transistors for low-cost RF applications," IEEE Trans. Electron Devices 59, 2296-2301 (2012).

M. J. Kumar, S. Janardhanan, "Doping-less tunnel field effect transistor: Design and investigation," IEEE Trans. Electron Devices 60, 3285-3290 (2013).

A. J. Walker, "Sub-50-nm dual-gate thin-film transistors for monolithic 3-D flash," IEEE Trans. Electron Devices 56, 2703-2710 (2009).

C. A. Dimitriadis, P. A. Coxon, N. A. Economou, "Leakage current of undoped LPCVD polycrystalline silicon thin-film transistors," IEEE Trans. Electron Devices 42, 950-956 (1995).

IEEE Electron Device Lett. (1)

J. C. Sturm, J. F. Gibbons, "Vertical bipolar transistors in laser-recrystallized polysilicon," IEEE Electron Device Lett. 6, 400-402 (1985).

IEEE Electron Device Lett. (4)

B.-Y. Tsaur, D. J. Silversmith, J. C. C. Fan, R. W. Mountain, "Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on ${{SiO}}_{2}$ ," IEEE Electron Device Lett. 4, 269-271 (1983).

T. Tsai, K. M. Chen, H. C. Lin, T. Y. Lin, C. J. Su, T. S. Chao, T. Y. Huang, "Low-operating-voltage ultrathin junctionless poly-Si thin-film transistor technology for RF applications," IEEE Electron Device Lett. 33, 1565-1567 (2012).

B. Rajasekharan, R. J. E. Hueting, C. Salm, T. van Hemert, R. A. M. Wolters, J. Schmitz, "Fabrication and characterization of the charge-plasma diode," IEEE Electron Device Lett. 31, 528-530 (2010).

R. J. E. Hueting, B. Rajasekharan, C. Salm, J. Schmitz, "The charge plasma p-n diode," IEEE Electron Device Lett. 29, 1367-1369 (2008).

IEEE Trans. Computer-Aided Des. Integr. Circuits Syst. (1)

C. Lombardi, S. Manzini, A. Saporito, M. Vanzi, "A physically based mobility model for numerical simulation of nonplanar devices," IEEE Trans. Computer-Aided Des. Integr. Circuits Syst. 7, 1164-1171 (1988).

IEEE Trans. Device Mater. Rel. (1)

M. J. Kumar, V. Parihar, "Surface Accumulation Layer Transistor (SALTran): A new bipolar transistor for enhanced current gain and reduced hot-carrier degradation," IEEE Trans. Device Mater. Rel. 4, 509-515 (2004).

IEEE Trans. Electron Devices (2)

S.-Y. Kim, S. Baytok, K. Roy, "Thin-BOX poly-Si thin-film transistors for CMOS-compatible analog operations," IEEE Trans. Electron Devices 58, 1687-1695 (2011).

M. Kimura, I. Yudasaka, S. Kanbe, H. Kobayashi, H. Kiguchi, S. Seki, S. Miyashita, T. Shimoda, T. Ozawa, K. Kitawada, T. Nakazawa, W. Miyazawa, H. Ohshima, "Low-temperature polysilicon thin-film transistor driving with integrated driver for high-resolution light emitting polymer display," IEEE Trans. Electron Devices 46, 2282-2288 (1999).

IEEE Trans. Electron Devices (1)

M. J. Kumar, K. Nadda, "Bipolar charge plasma transistor: A novel three terminal device," IEEE Trans. Electron Devices 59, 962-967 (2012).

IEEE Trans. Electron Devices (5)

R. Guerrieri, P. Ciampolini, A. Gnudi, M. Rudan, G. Baccarani, "Numerical simulation of polycrystalline-Silicon MOSFET's," IEEE Trans. Electron Devices 33, 1201-1206 (1986).

T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanaka, N. Hashimoto, A. Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda, T. Nagano, "Advanced TFT SRAM cell technology using a phase-shift lithography," IEEE Trans. Electron Devices 42, 1305-1313 (1995).

P. M. Walker, H. Mizuta, S. Uno, Y. Furuta, D. G. Hasko, "Improved off-current and subthreshold slope in aggressively scaled poly-Si TFTs with a single grain boundary in the channel," IEEE Trans. Electron Devices 51, 212-219 (2004).

C.-H. Ho, G. Panagopoulos, K. Roy, "A physical model for grain-boundary-induced threshold voltage variation in polysilicon thin-film transistors," IEEE Trans. Electron Devices 59, 2396-2402 (2012).

M. J. Kumar, P. Singh, "A super beta bipolar transistor using SiGe-base Surface Accumulation Layer Transistor (SALTran) concept: A simulation study," IEEE Trans. Electron Devices 53, 577-579 (2006).

IEEE Trans. on Electron Devices (1)

K. Nadda, M. J. Kumar, "Schottky collector bipolar transistor without impurity doped emitter and base: Design and performance," IEEE Trans. on Electron Devices 60, 2956-2959 (2013).

J. Appl. Phys. (1)

C. A. Dimitriadis, D. H. Tassis, N. A. Economou, A. J. Lowe, "Determination of bulk states and interface states distributions in polycrystalline silicon thin-film transistors," J. Appl. Phys. 74, 2919-2924 (1993).

J. Mater. Science in Semicond. Process. (1)

G. Fortunato, A. Pecora, L. Maiolo, "Poly-silicon thin-film transistors on polymer substrates," J. Mater. Science in Semicond. Process. 15, 627-641 (2012).

J. Non-Cryst. Solids (1)

T. Mohammad-Brahim, K. Kis-Sion, D. Briand, M. Sarret, O. Bonnaud, J. P. Kleider, C. Longeaud, B. Lambert, "From amorphous to polycrystalline thin films: Dependence on annealing time of structural and electronic properties," J. Non-Cryst. Solids 227–230, 962-966 (1998).

Jpn. J. Appl. Phys. (2)

P. M. Walker, U. Shigeyasu, H. Mizuta, "Simulation study of the dependence of submicron polysilicon thin-film transistor output characteristics on grain boundary position," Jpn. J. Appl. Phys. 44, 8322-8328 (2005).

K. Yamaguchi, "Modeling and characterization of polycrystalline-silicon thin-film transistors with a channel-length comparable to a grain size," Jpn. J. Appl. Phys. 89, 590-595 (2001).

Microelectronics Reliability (1)

N. A. Hastas, N. Archontas, C. A. Dimitriadis, G. Kamarinos, T. Nikolaidis, N. Georgoulas, A. Thanailakis, "Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors," Microelectronics Reliability 45, 341-348 (2005).

Proc. IEEE (1)

K. Banerjee, S. J. Souri, P. Kapur, K. C. Saraswat, "3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proc. IEEE 89, 602-633 (2001).

Other (8)

T. Tanaka, H. Asuma, K. Ogawa, Y. Shinagawa, N. Konishi, "An LCD addressed by a-Si:H TFTs with peripheral poly-Si TFT circuits," IEDM Tech. Dig. (1993) pp. 389-392.

S. Y. Kim, W. F. Loke, S. P. Park, B. Jung, K. Roy, "Poly-Si thin film transistors: Opportunities for low-cost RF applications," IEEE Intern. Conf. IC Design & Technology (ICICDT) (2012) pp. 1-4.

G. Kawachi, T. Okada, S. Tsuboi, M. Mitani, "Sub-micron CMOS/MOS-bipolar hybrid TFTs for system displays," IEDM Tech. Dig. (2007) pp. 591-594.

C. Y. Chang, B. S. Wu, Y. K. Fang, R. H. Lee, "Amorphous silicon bipolar transistor with high gain ( $> 12$ ) and high speed ( $> {{30}}~{{ps}}$ )," IEDM Tech. Dig. (1985) pp. 432-435.

ATLAS Device Simulation Software Silvaco Int.Santa ClaraCAUSA (2012).

S. Selberherr, Analysis and Simulation of Semiconductor Devices (Springer-Verlag, 1984).

L. Yiming, J. Y. Huang, B.-S. Lee, C.-H. Hwang, "Effect of single grain boundary position on surrounding-gate polysilicon thin film transistors," 7th IEEE Conf. Nanotechnol. (2007) pp. 1148-1151.

T. C. Liu, J. B. Kuo, "Grain boundary-related kink effects of poly-Si TFTs," IEEE Int. Conf. Electron Devices and Solid State Circuit (EDSSC) (2012) pp. 1-2.

Cited By

OSA participates in CrossRef's Cited-By Linking service. Citing articles from OSA journals and other participating publishers are listed here.