This work reports an integration process for hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) backplanes on flexible plastic substrates that attempts to reduce the large misalignment between the successive patterned layers in fabrication. Here, a double-sided adhesive tape is used to attach the plastic substrate to a rigid carrier. The results indicate a reduction of overlay misalignment from 22 μm on free-standing foil to 2 μm when laminated to a rigid carrier for five consecutive mask layers. Electrical characteristics of the fabricated a-Si:H TFTs on 3′′ round plastic substrates show an ON/OFF current ratio of over 10<sup>8</sup>, field-effect mobility of 0.8 0.8 cm<sup>2</sup>/V · s, and gate leakage current of 10<sup>-13</sup> A.
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