Abstract

This work reports an integration process for hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) backplanes on flexible plastic substrates that attempts to reduce the large misalignment between the successive patterned layers in fabrication. Here, a double-sided adhesive tape is used to attach the plastic substrate to a rigid carrier. The results indicate a reduction of overlay misalignment from 22 μm on free-standing foil to 2 μm when laminated to a rigid carrier for five consecutive mask layers. Electrical characteristics of the fabricated a-Si:H TFTs on 3′′ round plastic substrates show an ON/OFF current ratio of over 10<sup>8</sup>, field-effect mobility of 0.8 0.8 cm<sup>2</sup>/V · s, and gate leakage current of 10<sup>-13</sup> A.

© 2012 IEEE

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  1. G. P. Crawford, Flexible Flat Panel Displays (Wiley, 2005).
  2. I. Chan, M. Moradi, A. Sazonov, A. Nathan, , "150 °C amorphous silicon thin film transistors with low- stress nitride on transparent plastic," J. Display Tech. 7, 36-39 (2011).
  3. A. Sazonov, D. Striakhilev, C.-H. Lee, A. Nathan, "Low-temperature materials and thin film transistors for flexible electronics," Proc. IEEE 93, 1420-1428 (2005).
  4. A. Sazonov, M. Meitine, D. Striakhilev, A. Nathan, "Low-temperature materials and thin film transistors for electronics on flexible substrates," Phys. Sem. Dev. 40, 959967 (2005).
  5. P. G. LeComber, "Applications and defects in amorphous silicon," J. Non-Crystalline Solids 90, 219-228 (1987).
  6. K. H. Cherenack, A. Z. Kattamis, B. Hekmatshoar, J. C. Sturm, S. Wagner, "Self-aligned amorphous silicon thin film transistors with mobility above 1 ${\hbox{cm}}^{2}\cdot{\hbox{V}}^{-1}\cdot{\hbox{s}}^{-1}$fabricated at 300 $\deg{\hbox{C}}$ on clear plastic substrates," Mater. Res. Soc. Symp. Proc. 1066, 471-476 (2008).
  7. M. J. Powell, C. Glasse, P. W. Green, I. D. French, I. J. Stemp, "An amorphous silicon thin-film transistor with fully self-aligned top gate structure," IEEE Electron Device Lett. 21, 104-106 (2000).
  8. H. H. Busta, J. E. Pogemiller, R. W. Standley, K. D. Mackenzie, "Self-aligned bottom-gate submicrometer channel length a-Si:H thin-film transistors," IEEE Trans. Electron Devices 36, 2883-2888 (1989).
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  13. D. Loy, Y. K. Lee, C. Bell, M. Richards, E. Bawolek, S. Ageno, C. Moyer, M. Marrs, S. M. Venugopal, J. Kaminski, N. Colaneri, S. M. O'Rourke, "Active matrix PHOLED displays on temporary bonded polyethylene naphthalate substrates with 1800 $\deg{\hbox{C}}$ a-Si:H TFTs," SID Dig. (2009) pp. 988-991.
  14. I. Yakimets, M. Barink, M. Goorhuis, P. Giesen, F. Furthner, E. Meinders, "Micro-deformation of flexible substrate for electronic devices during handling prior to lithography patterning," Microelectron. Eng. 87, 641-647 (2010).
  15. Teijin DuPont Films“Teonex Q65F: Technical Data,” (2010).
  16. Teijin DuPont Films Japan“PEN Film: Teonex,” (2003–2008) http://www.teijindupontfilms.jp/english/product/pen_teo.html.
  17. A. Sazonov, A. Nathan, "1200 $^{\deg}{\hbox{C}}$ fabrication technology for a-Si:H film transistors on flexible polyimide substrates," J. Vac. Sci. Technol. A 2, 780-782 (2000).
  18. A. Sazonov, C. McArthur, "Sub-100 $^{\deg}{\hbox{C}}$ a-Si:H thin-film transistors on plastic substrates with silicon nitride gate dielectrics," J. Vac. Sci. Technol. A 22, 2052-2055 (2004).

2011 (1)

I. Chan, M. Moradi, A. Sazonov, A. Nathan, , "150 °C amorphous silicon thin film transistors with low- stress nitride on transparent plastic," J. Display Tech. 7, 36-39 (2011).

2010 (1)

I. Yakimets, M. Barink, M. Goorhuis, P. Giesen, F. Furthner, E. Meinders, "Micro-deformation of flexible substrate for electronic devices during handling prior to lithography patterning," Microelectron. Eng. 87, 641-647 (2010).

2008 (1)

K. H. Cherenack, A. Z. Kattamis, B. Hekmatshoar, J. C. Sturm, S. Wagner, "Self-aligned amorphous silicon thin film transistors with mobility above 1 ${\hbox{cm}}^{2}\cdot{\hbox{V}}^{-1}\cdot{\hbox{s}}^{-1}$fabricated at 300 $\deg{\hbox{C}}$ on clear plastic substrates," Mater. Res. Soc. Symp. Proc. 1066, 471-476 (2008).

2005 (2)

A. Sazonov, D. Striakhilev, C.-H. Lee, A. Nathan, "Low-temperature materials and thin film transistors for flexible electronics," Proc. IEEE 93, 1420-1428 (2005).

A. Sazonov, M. Meitine, D. Striakhilev, A. Nathan, "Low-temperature materials and thin film transistors for electronics on flexible substrates," Phys. Sem. Dev. 40, 959967 (2005).

2004 (3)

W. S. Wong, K. E. Paul, R. A. Street, "Digital-lithographic processing for thin-film transistor array fabrication," J. Non-Crystalline Solids 338–340, 710-714 (2004).

F. Lemmi, W. Chung, S. Lin, P. M. Smith, T. Sasagawa, B. C. Drews, A. Hua, J. R. Stern, J. Y. Chen, "High-performance TFTs fabricated on plastic substrates," IEEE Electron Device Lett. 25, 486-488 (2004).

A. Sazonov, C. McArthur, "Sub-100 $^{\deg}{\hbox{C}}$ a-Si:H thin-film transistors on plastic substrates with silicon nitride gate dielectrics," J. Vac. Sci. Technol. A 22, 2052-2055 (2004).

2000 (2)

A. Sazonov, A. Nathan, "1200 $^{\deg}{\hbox{C}}$ fabrication technology for a-Si:H film transistors on flexible polyimide substrates," J. Vac. Sci. Technol. A 2, 780-782 (2000).

M. J. Powell, C. Glasse, P. W. Green, I. D. French, I. J. Stemp, "An amorphous silicon thin-film transistor with fully self-aligned top gate structure," IEEE Electron Device Lett. 21, 104-106 (2000).

1998 (1)

D. B. Thomasson, T. N. Jackson, "Fully self-aligned trilayer a-Si:H thin-film transistors with deposited doped contact layer," IEEE Electron Device Lett. 19, 124-126 (1998).

1989 (1)

H. H. Busta, J. E. Pogemiller, R. W. Standley, K. D. Mackenzie, "Self-aligned bottom-gate submicrometer channel length a-Si:H thin-film transistors," IEEE Trans. Electron Devices 36, 2883-2888 (1989).

1987 (1)

P. G. LeComber, "Applications and defects in amorphous silicon," J. Non-Crystalline Solids 90, 219-228 (1987).

IEEE Electron Device Lett. (3)

M. J. Powell, C. Glasse, P. W. Green, I. D. French, I. J. Stemp, "An amorphous silicon thin-film transistor with fully self-aligned top gate structure," IEEE Electron Device Lett. 21, 104-106 (2000).

D. B. Thomasson, T. N. Jackson, "Fully self-aligned trilayer a-Si:H thin-film transistors with deposited doped contact layer," IEEE Electron Device Lett. 19, 124-126 (1998).

F. Lemmi, W. Chung, S. Lin, P. M. Smith, T. Sasagawa, B. C. Drews, A. Hua, J. R. Stern, J. Y. Chen, "High-performance TFTs fabricated on plastic substrates," IEEE Electron Device Lett. 25, 486-488 (2004).

IEEE Trans. Electron Devices (1)

H. H. Busta, J. E. Pogemiller, R. W. Standley, K. D. Mackenzie, "Self-aligned bottom-gate submicrometer channel length a-Si:H thin-film transistors," IEEE Trans. Electron Devices 36, 2883-2888 (1989).

J. Display Tech. (1)

I. Chan, M. Moradi, A. Sazonov, A. Nathan, , "150 °C amorphous silicon thin film transistors with low- stress nitride on transparent plastic," J. Display Tech. 7, 36-39 (2011).

J. Non-Crystalline Solids (2)

P. G. LeComber, "Applications and defects in amorphous silicon," J. Non-Crystalline Solids 90, 219-228 (1987).

W. S. Wong, K. E. Paul, R. A. Street, "Digital-lithographic processing for thin-film transistor array fabrication," J. Non-Crystalline Solids 338–340, 710-714 (2004).

J. Vac. Sci. Technol. A (2)

A. Sazonov, A. Nathan, "1200 $^{\deg}{\hbox{C}}$ fabrication technology for a-Si:H film transistors on flexible polyimide substrates," J. Vac. Sci. Technol. A 2, 780-782 (2000).

A. Sazonov, C. McArthur, "Sub-100 $^{\deg}{\hbox{C}}$ a-Si:H thin-film transistors on plastic substrates with silicon nitride gate dielectrics," J. Vac. Sci. Technol. A 22, 2052-2055 (2004).

Mater. Res. Soc. Symp. Proc. (1)

K. H. Cherenack, A. Z. Kattamis, B. Hekmatshoar, J. C. Sturm, S. Wagner, "Self-aligned amorphous silicon thin film transistors with mobility above 1 ${\hbox{cm}}^{2}\cdot{\hbox{V}}^{-1}\cdot{\hbox{s}}^{-1}$fabricated at 300 $\deg{\hbox{C}}$ on clear plastic substrates," Mater. Res. Soc. Symp. Proc. 1066, 471-476 (2008).

Microelectron. Eng. (1)

I. Yakimets, M. Barink, M. Goorhuis, P. Giesen, F. Furthner, E. Meinders, "Micro-deformation of flexible substrate for electronic devices during handling prior to lithography patterning," Microelectron. Eng. 87, 641-647 (2010).

Phys. Sem. Dev. (1)

A. Sazonov, M. Meitine, D. Striakhilev, A. Nathan, "Low-temperature materials and thin film transistors for electronics on flexible substrates," Phys. Sem. Dev. 40, 959967 (2005).

Proc. IEEE (1)

A. Sazonov, D. Striakhilev, C.-H. Lee, A. Nathan, "Low-temperature materials and thin film transistors for flexible electronics," Proc. IEEE 93, 1420-1428 (2005).

Other (5)

G. P. Crawford, Flexible Flat Panel Displays (Wiley, 2005).

Teijin DuPont Films“Teonex Q65F: Technical Data,” (2010).

Teijin DuPont Films Japan“PEN Film: Teonex,” (2003–2008) http://www.teijindupontfilms.jp/english/product/pen_teo.html.

A. C. Arias, J. Daniel, S. Sambandan, T. N. Ng, B. Russo, B. Krusor, R. A. Street, "All printed thin film transistors for flexible electronics," Proc. SPIE (2008) pp. 70540L-1-7.

D. Loy, Y. K. Lee, C. Bell, M. Richards, E. Bawolek, S. Ageno, C. Moyer, M. Marrs, S. M. Venugopal, J. Kaminski, N. Colaneri, S. M. O'Rourke, "Active matrix PHOLED displays on temporary bonded polyethylene naphthalate substrates with 1800 $\deg{\hbox{C}}$ a-Si:H TFTs," SID Dig. (2009) pp. 988-991.

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