Abstract

A new process enabling the transfer of a single-crystal silicon film to a glass substrate has been developed allowing for the creation of fully crystalline thin-film silicon-on-glass (SiOG) transistors. The dominant 2-D effect in SiOG transistors results from fringing electric field lines emanating through the glass substrate between the source, drain, and thin-film channel regions. The fringing field leads to a shift in the flatband or threshold voltage in a similar manner to drain-induced barrier lowering. The fringing field effect can lead to an 11% shift in flatband for devices with channel length of 4 $\mu{\rm m}$ and a nominal flatband of $-$1 V. A compact model for the fringing field in these devices has been developed using conformal mapping techniques that capture the dependence on both channel length and the relative size of the source and drain electrodes. The model accurately predicts the influence of the fringing field on subthreshold drain current for SiOG PFETs operating in accumulation. The model is validated against the 2-D device simulator Silvaco Atlas.

© 2010 IEEE

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  1. R. G. Manley, G. Fenger, K. Hirschman, J. Couillard, C. Kosik Williams, D. Dawson-Elli, J. Cites, "Demonstration of high performance TFTs on silicon on glass (SiOG) substrate," SID 2007 Dig. pp. 287-289.
  2. T. Ernst, S. Cristoloveanu, "Buried oxide fringing capacitance: A new physical model and its implication on SOI device scaling and architecture," Proc. 1999 IEEE Int. SOI Conf. (1999) pp. 38-39.
  3. C. J. Nassar, J. F. Revelli, Jr.C. A. K. Williams, R. J. Bowman, "A charge-based compact model core for thin-film monocrystalline silicon on glass PMOSFETs operated in accumulation," J. Display Technol. 6, 306-311 (2010).
  4. C. J. Nassar, C. A. K. Williams, D. Dawson-Elli, R. J. Bowman, "Single Fermi level thin-film CMOS on glass: The behavior of enhancement-mode PMOSFETs from cutoff through accumulation," IEEE Trans. Electron Devices 56, 1974-1979 (2009).
  5. P. C. Yeh, J. G. Fossum, "Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology," IEEE Trans. Electron Devices 42, 1605-1613 (1995).
  6. H.-O. Joachim, Y. Yamagushi, K. Ishikawa, Y. Inoue, T. Nishimura, "Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFET's down to 0.1," IEEE Trans. Electron Devices 40, 1812-1817 (1993).
  7. T. Ernst, R. Ritzenthaler, O. Faynot, S. Cristoloveanu, "A model of fringing fields in short-channel planar and triple-gate SOI MOSFETs," IEEE Trans. Electron Devices 54, 1366-1375 (2007).
  8. H. C. Pao, C. T. Sah, "Effects of diffusion current on characteristics of metal-oxide (insulator)–semiconductor transistors," Solid State Electron. 9, 927-937 (1966).
  9. S. R. Banna, P. C. H. Chan, P. K. Ko, C. T. Nguyen, M. Chan, "Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's," IEEE Trans. Electron Devices 42, 1949-1955 (1995).
  10. T. K. Liu, “Impedances and field distributions of two coplanar parallel perfectly conducting strips with arbitrary widths,” AFWL Interaction notes, note 182 (1974).

2010 (1)

2009 (1)

C. J. Nassar, C. A. K. Williams, D. Dawson-Elli, R. J. Bowman, "Single Fermi level thin-film CMOS on glass: The behavior of enhancement-mode PMOSFETs from cutoff through accumulation," IEEE Trans. Electron Devices 56, 1974-1979 (2009).

2007 (1)

T. Ernst, R. Ritzenthaler, O. Faynot, S. Cristoloveanu, "A model of fringing fields in short-channel planar and triple-gate SOI MOSFETs," IEEE Trans. Electron Devices 54, 1366-1375 (2007).

1995 (2)

S. R. Banna, P. C. H. Chan, P. K. Ko, C. T. Nguyen, M. Chan, "Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's," IEEE Trans. Electron Devices 42, 1949-1955 (1995).

P. C. Yeh, J. G. Fossum, "Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology," IEEE Trans. Electron Devices 42, 1605-1613 (1995).

1993 (1)

H.-O. Joachim, Y. Yamagushi, K. Ishikawa, Y. Inoue, T. Nishimura, "Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFET's down to 0.1," IEEE Trans. Electron Devices 40, 1812-1817 (1993).

1966 (1)

H. C. Pao, C. T. Sah, "Effects of diffusion current on characteristics of metal-oxide (insulator)–semiconductor transistors," Solid State Electron. 9, 927-937 (1966).

IEEE Trans. Electron Devices (5)

C. J. Nassar, C. A. K. Williams, D. Dawson-Elli, R. J. Bowman, "Single Fermi level thin-film CMOS on glass: The behavior of enhancement-mode PMOSFETs from cutoff through accumulation," IEEE Trans. Electron Devices 56, 1974-1979 (2009).

P. C. Yeh, J. G. Fossum, "Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology," IEEE Trans. Electron Devices 42, 1605-1613 (1995).

H.-O. Joachim, Y. Yamagushi, K. Ishikawa, Y. Inoue, T. Nishimura, "Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFET's down to 0.1," IEEE Trans. Electron Devices 40, 1812-1817 (1993).

T. Ernst, R. Ritzenthaler, O. Faynot, S. Cristoloveanu, "A model of fringing fields in short-channel planar and triple-gate SOI MOSFETs," IEEE Trans. Electron Devices 54, 1366-1375 (2007).

S. R. Banna, P. C. H. Chan, P. K. Ko, C. T. Nguyen, M. Chan, "Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's," IEEE Trans. Electron Devices 42, 1949-1955 (1995).

J. Display Technol. (1)

Solid State Electron. (1)

H. C. Pao, C. T. Sah, "Effects of diffusion current on characteristics of metal-oxide (insulator)–semiconductor transistors," Solid State Electron. 9, 927-937 (1966).

Other (3)

T. K. Liu, “Impedances and field distributions of two coplanar parallel perfectly conducting strips with arbitrary widths,” AFWL Interaction notes, note 182 (1974).

R. G. Manley, G. Fenger, K. Hirschman, J. Couillard, C. Kosik Williams, D. Dawson-Elli, J. Cites, "Demonstration of high performance TFTs on silicon on glass (SiOG) substrate," SID 2007 Dig. pp. 287-289.

T. Ernst, S. Cristoloveanu, "Buried oxide fringing capacitance: A new physical model and its implication on SOI device scaling and architecture," Proc. 1999 IEEE Int. SOI Conf. (1999) pp. 38-39.

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