Abstract

In this paper, we propose a new hardware architecture implemented as a very large scaled integrated circuit by using an application-specific integrated circuit technology, where block-based calculations are used to generate holograms. The proposed hardware is structured to produce a part of a hologram in the block units in parallel. A block of a hologram is calculated using an object point, and then the calculation is repeated for all object points to obtain intermediate results that are accumulated to produce the final block of a hologram. This structure can be used to produce holograms of various sizes in real time with optimized memory access. The proposed hardware was implemented using the Hynix 0.18 μm CMOS technology of Magna Chip, Inc., and it has about 448 K gate counts and a silicon size of 3.592  mm×3.592  mm. It can generate complex holograms and operate in a stable manner at a clock frequency of 200 MHz.

© 2017 Optical Society of America

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