Abstract

This paper presents a proposal of an optical configuration acceleration method applied to optically reconfigurable gate arrays (ORGAs) using a negative logic implementation. The gate array of an ORGA is reconfigured using a holographic memory. The reading time of a holographic memory depends on the number of bright bits included in a configuration context. The proposed optical configuration acceleration method can decrease the number of bright bits. As a result, the proposed optical configuration acceleration method can increase the reconfiguration frequency. In this paper, a fabricated ORGA very large scale integration that can support the optical configuration acceleration method is estimated. Consequently, this paper shows that the reconfiguration frequency of the proposed method is 1.97 times higher than those of conventional ORGA architectures with no increase of laser power.

© 2013 Optical Society of America

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    [CrossRef]
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  11. H. Morita and M. Watanabe, “Microelectromechanical configuration of an optically reconfigurable gate array,” IEEE J. Quantum Electron. 46, 1288–1294 (2010).
    [CrossRef]
  12. M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” IEEE/OSA J. Lightw. Technol. 27, 4460–4470 (2009).
    [CrossRef]
  13. D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
    [CrossRef]
  14. M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515(2006).
    [CrossRef]

2010 (1)

H. Morita and M. Watanabe, “Microelectromechanical configuration of an optically reconfigurable gate array,” IEEE J. Quantum Electron. 46, 1288–1294 (2010).
[CrossRef]

2009 (2)

M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” IEEE/OSA J. Lightw. Technol. 27, 4460–4470 (2009).
[CrossRef]

P. Mal, P. D. Patel, and F. R. Beyette, “Design and demonstration of a fully integrated multi-technology FPGA: a reconfigurable architecture for photonic and other multi-technology applications,” IEEE Trans. Circuit. Sys. 56, 1182–1191 (2009).
[CrossRef]

2008 (1)

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
[CrossRef]

2006 (1)

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515(2006).
[CrossRef]

1999 (1)

J. V. Campenhout, H. V. Marck, J. Depreitere, and J. Dambre, “Optoelectronic FPGA’s,” IEEE J. Sel. Top. Quantum Electron. 5, 306–315 (1999).
[CrossRef]

Allain, F.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Andreou, A. G.

E. Culurciello and A. G. Andreou, “Capacitive coupling of data and power for 3D silicon-on-insulator VLSI,” in IEEE International Symposium on Circuits and Systems (IEEE, 2005), pp. 4142–4145.

Andrieu, F.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Armstrong, M.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Auth, C.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Autran, J. L.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Barral, V.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Beyette, F. R.

P. Mal, P. D. Patel, and F. R. Beyette, “Design and demonstration of a fully integrated multi-technology FPGA: a reconfigurable architecture for photonic and other multi-technology applications,” IEEE Trans. Circuit. Sys. 56, 1182–1191 (2009).
[CrossRef]

Bohr, M.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Bost, M.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Brevard, L.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Breyer, F.

F. Breyer, S. C. J. Lee, D. Cardenas, S. Randel, and N. Hanik, “Real-time gigabit ethernet transmission over up to 25 m Step-Index Polymer Optical Fibre using LEDs and FPGA based signal processing, ” presented at European Conference on Optical Communication, Vienna, Austria, 20–24 September 2009.

Buj-Dufournet, C.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Campenhout, J. V.

J. V. Campenhout, H. V. Marck, J. Depreitere, and J. Dambre, “Optoelectronic FPGA’s,” IEEE J. Sel. Top. Quantum Electron. 5, 306–315 (1999).
[CrossRef]

Cardenas, D.

F. Breyer, S. C. J. Lee, D. Cardenas, S. Randel, and N. Hanik, “Real-time gigabit ethernet transmission over up to 25 m Step-Index Polymer Optical Fibre using LEDs and FPGA based signal processing, ” presented at European Conference on Optical Communication, Vienna, Austria, 20–24 September 2009.

Cayrefourcq, I.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Charvat, P.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Culurciello, E.

E. Culurciello and A. G. Andreou, “Capacitive coupling of data and power for 3D silicon-on-insulator VLSI,” in IEEE International Symposium on Circuits and Systems (IEEE, 2005), pp. 4142–4145.

Dambre, J.

J. V. Campenhout, H. V. Marck, J. Depreitere, and J. Dambre, “Optoelectronic FPGA’s,” IEEE J. Sel. Top. Quantum Electron. 5, 306–315 (1999).
[CrossRef]

Daval, N.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Deleonibus, S.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Depreitere, J.

J. V. Campenhout, H. V. Marck, J. Depreitere, and J. Dambre, “Optoelectronic FPGA’s,” IEEE J. Sel. Top. Quantum Electron. 5, 306–315 (1999).
[CrossRef]

Ernst, T.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Faynot, O.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Fenouillet-Beranger, C.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Flach, G.

R. Hentschke, G. Flach, F. Pinto, and R. Reis, “3D-Vias aware quadratic placement for 3D VLSI circuits,” in IEEE Computer Society Annual Symposium on VLSI (IEEE, 2007), pp. 67–72.

Ghani, T.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Glass, G.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Hanik, N.

F. Breyer, S. C. J. Lee, D. Cardenas, S. Randel, and N. Hanik, “Real-time gigabit ethernet transmission over up to 25 m Step-Index Polymer Optical Fibre using LEDs and FPGA based signal processing, ” presented at European Conference on Optical Communication, Vienna, Austria, 20–24 September 2009.

Hartmann, J. M.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Hentschke, R.

R. Hentschke, G. Flach, F. Pinto, and R. Reis, “3D-Vias aware quadratic placement for 3D VLSI circuits,” in IEEE Computer Society Annual Symposium on VLSI (IEEE, 2007), pp. 67–72.

Hoffmann, T.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Johnson, K.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Kenyon, C.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Klaus, J.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Kobayashi, F.

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515(2006).
[CrossRef]

Lafond, D.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Lee, S. C. J.

F. Breyer, S. C. J. Lee, D. Cardenas, S. Randel, and N. Hanik, “Real-time gigabit ethernet transmission over up to 25 m Step-Index Polymer Optical Fibre using LEDs and FPGA based signal processing, ” presented at European Conference on Optical Communication, Vienna, Austria, 20–24 September 2009.

Mal, P.

P. Mal, P. D. Patel, and F. R. Beyette, “Design and demonstration of a fully integrated multi-technology FPGA: a reconfigurable architecture for photonic and other multi-technology applications,” IEEE Trans. Circuit. Sys. 56, 1182–1191 (2009).
[CrossRef]

Marck, H. V.

J. V. Campenhout, H. V. Marck, J. Depreitere, and J. Dambre, “Optoelectronic FPGA’s,” IEEE J. Sel. Top. Quantum Electron. 5, 306–315 (1999).
[CrossRef]

McIntyre, B.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Mistry, K.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Morita, H.

H. Morita and M. Watanabe, “Microelectromechanical configuration of an optically reconfigurable gate array,” IEEE J. Quantum Electron. 46, 1288–1294 (2010).
[CrossRef]

Munteanu, D.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Murthy, A.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Nakajima, M.

M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” IEEE/OSA J. Lightw. Technol. 27, 4460–4470 (2009).
[CrossRef]

Patel, P. D.

P. Mal, P. D. Patel, and F. R. Beyette, “Design and demonstration of a fully integrated multi-technology FPGA: a reconfigurable architecture for photonic and other multi-technology applications,” IEEE Trans. Circuit. Sys. 56, 1182–1191 (2009).
[CrossRef]

Pinto, F.

R. Hentschke, G. Flach, F. Pinto, and R. Reis, “3D-Vias aware quadratic placement for 3D VLSI circuits,” in IEEE Computer Society Annual Symposium on VLSI (IEEE, 2007), pp. 67–72.

Poiroux, T.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Randel, S.

F. Breyer, S. C. J. Lee, D. Cardenas, S. Randel, and N. Hanik, “Real-time gigabit ethernet transmission over up to 25 m Step-Index Polymer Optical Fibre using LEDs and FPGA based signal processing, ” presented at European Conference on Optical Communication, Vienna, Austria, 20–24 September 2009.

Reis, R.

R. Hentschke, G. Flach, F. Pinto, and R. Reis, “3D-Vias aware quadratic placement for 3D VLSI circuits,” in IEEE Computer Society Annual Symposium on VLSI (IEEE, 2007), pp. 67–72.

Sandford, J.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Seto, D.

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
[CrossRef]

Silberstein, M.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Sivakumar, S.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Smith, P.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Thompson, S.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

Tosti, L.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Vidal, V.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

Watanabe, M.

H. Morita and M. Watanabe, “Microelectromechanical configuration of an optically reconfigurable gate array,” IEEE J. Quantum Electron. 46, 1288–1294 (2010).
[CrossRef]

M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” IEEE/OSA J. Lightw. Technol. 27, 4460–4470 (2009).
[CrossRef]

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
[CrossRef]

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515(2006).
[CrossRef]

Zawadzki, K.

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

IEEE J. Quantum Electron. (2)

H. Morita and M. Watanabe, “Microelectromechanical configuration of an optically reconfigurable gate array,” IEEE J. Quantum Electron. 46, 1288–1294 (2010).
[CrossRef]

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
[CrossRef]

IEEE J. Sel. Top. Quantum Electron. (1)

J. V. Campenhout, H. V. Marck, J. Depreitere, and J. Dambre, “Optoelectronic FPGA’s,” IEEE J. Sel. Top. Quantum Electron. 5, 306–315 (1999).
[CrossRef]

IEEE Trans. Circuit. Sys. (1)

P. Mal, P. D. Patel, and F. R. Beyette, “Design and demonstration of a fully integrated multi-technology FPGA: a reconfigurable architecture for photonic and other multi-technology applications,” IEEE Trans. Circuit. Sys. 56, 1182–1191 (2009).
[CrossRef]

IEEE/OSA J. Lightw. Technol. (1)

M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” IEEE/OSA J. Lightw. Technol. 27, 4460–4470 (2009).
[CrossRef]

Jpn. J. Appl. Phys. (1)

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515(2006).
[CrossRef]

Other (8)

F. Breyer, S. C. J. Lee, D. Cardenas, S. Randel, and N. Hanik, “Real-time gigabit ethernet transmission over up to 25 m Step-Index Polymer Optical Fibre using LEDs and FPGA based signal processing, ” presented at European Conference on Optical Communication, Vienna, Austria, 20–24 September 2009.

Altera Corporation, “Altera unveils 28 nm Stratix V FPGA family,” http://www.altera.com .

X. Wu, P. Gopalan, and G. Lara, “Xilinx next generation 28 nm FPGA technology overview,” http://www.xilinx.com .

Xilinx Inc., “Xilinx product data sheets,” http://www.xilinx.com .

T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, “A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors,” in IEEE International Electron Devices Meeting (IEEE, 2003), pp. 11.6.1–11.6.3.

V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J. M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J. L. Autran, and S. Deleonibus, “Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack,” in IEEE International Electron Devices Meeting (IEEE, 2007), pp. 61–64.

E. Culurciello and A. G. Andreou, “Capacitive coupling of data and power for 3D silicon-on-insulator VLSI,” in IEEE International Symposium on Circuits and Systems (IEEE, 2005), pp. 4142–4145.

R. Hentschke, G. Flach, F. Pinto, and R. Reis, “3D-Vias aware quadratic placement for 3D VLSI circuits,” in IEEE Computer Society Annual Symposium on VLSI (IEEE, 2007), pp. 67–72.

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Figures (13)

Fig. 1.
Fig. 1.

Basic construction of an ORGA.

Fig. 2.
Fig. 2.

Light intensity of each bit of optical configuration context diffracted from a holographic memory. Panels (a) and (d) show the light intensity of a configuration context including a single bright bit. Panels (b) and (e) show the light intensity of a configuration context including 12 bright bits. Panels (c) and (f) show the light intensity of a configuration context including 23 bright bits.

Fig. 3.
Fig. 3.

Negative logic implementation.

Fig. 4.
Fig. 4.

Photograph of a 0.18 μm CMOS process ORGA-VLSI.

Fig. 5.
Fig. 5.

CAD layout of a photodiode cell.

Fig. 6.
Fig. 6.

Block diagram and CAD layout of an ORLB.

Fig. 7.
Fig. 7.

Block diagram and CAD layout of an ORSM.

Fig. 8.
Fig. 8.

Block diagram of an experimental system.

Fig. 9.
Fig. 9.

Photograph of the experimental system.

Fig. 10.
Fig. 10.

Holographic memory patterns and CCD-captured configuration context patterns of OR circuits.

Fig. 11.
Fig. 11.

Holographic memory patterns and CCD-captured configuration context patterns of comparator circuits. In these circuits, when all values of three-bit or four-bit inputs are the same, the output becomes binary state low. Otherwise, the output becomes binary state high.

Fig. 12.
Fig. 12.

Holographic patterns and CCD-captured configuration context patterns of a comparator and larger than or equal operation circuits with two ports of two bits. In the comparator circuit of (a), when values of two ports are equal, the output becomes binary state high. Otherwise, the output becomes binary state low. In the larger than or equal operation, if one is larger than another or one is equal to another, the output becomes binary state high. Otherwise, the output becomes binary state low.

Fig. 13.
Fig. 13.

Hologram patterns and CCD-captured configuration context patterns of a three-bit down counter.

Tables (3)

Tables Icon

Table 1. Specifications of the ORGA-VLSI

Tables Icon

Table 2. Numbers of Bright Bits on Configuration Contexts

Tables Icon

Table 3. Configuration Times

Equations (3)

Equations on this page are rendered with MathJax. Learn more.

κnew=r=1[N2]r·CNr+r=[N2+1]N(Nr+1)·CNrr=1Nr·CNr.
H(x1,y1)O(x2,y2)cos(πλZL{(x1x2)2+(y1y2)2})dx2dy2.
H(x1,y1)=H(x1,y1)HminHmaxHmin.

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