Hardware implementation of pixel detection in gray-scale holographic data storage systems

Chi-Yun Chen; Tzi-Dar Chiueh

doi:10.1364/AO.51.008228

Hardware implementation of pixel detection in gray-scale holographic data storage systems

Chi-Yun Chen and Tzi-Dar Chiueh

Applied Optics
Vol. 51,
Issue 34,
pp. 8228-8235
(2012)
•https://doi.org/10.1364/AO.51.008228

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Chi-Yun Chen and Tzi-Dar Chiueh, "Hardware implementation of pixel detection in gray-scale holographic data storage systems," Appl. Opt. 51, 8228-8235 (2012)

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Related Topics
Table of Contents Category
- Optical Data Storage
Optics & Photonics Topics
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The topics in this list come from the OSA Optics and Photonics Topics applied to this article.
Previously assigned OCIS codes
- Holographic and volume memories (210.2860)
- Optical recording (210.4770)

About this Article
History
- Original Manuscript: August 2, 2012
- Manuscript Accepted: October 19, 2012
- Published: November 30, 2012

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Abstract

This paper presents hardware implementation of an efficient solution to recovering gray-scale data pixels of images that have undergone interpixel interference in holographic data storage systems. The adopted algorithm, called the turbo receiver using interference-aware dual-list (TRIDL) detection, enjoys benefits of low error rate performance and low complexity. To verify the functionality and feasibility, this paper implements TRIDL detection with some circuit design techniques such as resource sharing on a field-programmable gate array.

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Proposed Algorithm: IDL Detection
Input: ${λ_{a}}$ ; Output: ${λ}$
Phase 1: Interference generation
1:	$z_{base} ≔ QAM mapping (sgn ({λ_{a}}));$
2:	select $B = {b_{1}, b_{2}, \dots, b_{R_{t}}}$
3:	for $j = 0$ to $L_{z} - 1$ step 1
4:	$b_{z_{i}} (m) ≔ - b_{z_{base}} (m), m \in B_{j}$ *;
5:	$z_{j} ≔ QAM mapping ({b_{z_{j}}});$
6:	end
Phase 2: Cost update
7:	for $j = 0$ to $L_{z} - 1$ step 1
8:	for $i = 0$ to 7 step 1
9:	calculate cost by Eq. (4) for $(x_{i}; z_{j})$ ;
10:	update the bit-metric table;
11:	end
12:	end
13:	calculate output LLR by Eq. (7)

State	Tasks
IDLE	Idle
BASE	Prepare the BASE interference assumption
PREZ	PREpare interference ( $Z$ ) assumptions
CSTU	CoST Update
	Soft information generation
DONE	Finish updating

FPGA resource	Number of slices	29,509 (43%)
FPGA resource	Number of RAMB16s	8 (2%)
	Number of DSP48s	5 (5%)
Maximum frequency (MHz)		50
FPGA power (mW)	Clock	367
	Logic	5
	Signals	22
	Block RAMs	4
	IOs	7
	Leakage	1121
	Total	1526

IDL Detector IC Summary
Process	90 nm CMOS
Logic gate count	445 K
SRAM size (bits)	37 K
Core size	$1.13 mm \times 1.13 mm$
Die size	$1.62 mm \times 1.62 mm$
Clock speed	125 MHz
Power consumption at Vdd	124.6 mW at 0.9 V

SRAM Size (bits)
		$Q_{t}$
		0	1	2	3
$R_{t}$	4	372	580	892	1100
	8	372	788	2244	5156
	12	372	996	4428	15868
	16	372	1204	7444	36564
Gate Count
		$Q_{t}$
		0	1	2	3
$R_{t}$	4	270280	298981	298990	299658
	8	270280	299490	299545	300204
	12	270280	300026	300087	300803
	16	270280	300553	300592	301340
Throughput (Mbps)
		$Q_{t}$
		0	1	2	3
$R_{t}$	4	15.94	7.97	4.55	3.54
	8	15.94	5.31	1.59	0.66
	12	15.94	3.98	0.78	0.21
	16	15.94	3.19	0.46	0.09

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