Abstract

In this paper we propose a hardware architecture for high-speed computer-generated hologram generation that significantly reduces the number of memory access times to avoid the bottleneck in the memory access operation. For this, we use three main schemes. The first is pixel-by-pixel calculation, rather than light source-by-source calculation. The second is a parallel calculation scheme extracted by modifying the previous recursive calculation scheme. The last scheme is a fully pipelined calculation scheme and exactly structured timing scheduling, achieved by adjusting the hardware. The proposed hardware is structured to calculate a row of a computer-generated hologram in parallel and each hologram pixel in a row is calculated independently. It consists of and input interface, an initial parameter calculator, hologram pixel calculators, a line buffer, and a memory controller. The implemented hardware to calculate a row of a 1920×1080 computer-generated hologram in parallel uses 168,960 lookup tables, 153,944 registers, and 19,212 digital signal processing blocks in an Altera field programmable gate array environment. It can stably operate at 198 MHz. Because of three schemes, external memory bandwidth is reduced to approximately 1/20,000 of the previous ones at the same calculation speed.

© 2012 Optical Society of America

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References

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  1. T. Motoki, H. Isono, and I. Yuyama, “Present status of three-dimensional television research,” Proc. IEEE 83, 1009–1021 (1995).
    [CrossRef]
  2. J. K. Chung and M. H. Tsai, Three-Dimensional Holographic Imaging (Wiley, 2002).
  3. P. Hariharan, Basics of Holography (Cambridge University, 2002).
  4. M. Lucente, “Interactive computation of holograms using a look-up table,” J. Electron. Imaging 2, 28–34 (1993).
    [CrossRef]
  5. H. Yoshikawa, “Fast computation of Fresnel holograms employing difference,” Opt. Rev. 8, 331–335 (2001).
  6. T. Shimobaba and T. Ito, “An efficient computational method suitable for hardware of computer-generated hologram with phase computation by addition,” Comput. Phys. Commun. 138, 44–52 (2001).
    [CrossRef]
  7. N. Masuda, T. Ito, T. Tanaka, A. Shiraki, and T. Sugie, “Computer generated holography using a graphics processing unit,’’ Opt. Express 14, 603–608 (2006).
    [CrossRef]
  8. L. Ahrenberg, P. Benzie, M. Magnor, and J. Watson, “Computer generated holography using parallel commodity graphics hardware,” Opt. Express 14, 7636–7641 (2006).
    [CrossRef]
  9. Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, “Fast CGH computation using S-LUT on GPU,” Opt. Express 17, 18543–18555 (2009).
    [CrossRef]
  10. Y.-Z. Liu, J.-W. Dong, Y.-Y. Pu, B.-C. Chen, H.-X. He, and H.-Z. Wang, “High-speed full analytical holographic computations for true-life scenes,” Opt. Express 18, 3345–3351 (2010).
    [CrossRef]
  11. T. Shimobaba, T. Ito, N. Masuda, Y. Ichihashi, and N. Takada, “Fast calculation of computer-generated-hologram on AMD HD5000 series GPU and OpenCL,” Opt. Express 18, 9955–9960 (2010).
    [CrossRef]
  12. T. Ito, N. Masuda, K. Yoshimura, A. Shiraki, T. Shimobaba, and T. Sugie, “Special-purpose computer HORN-5 for a real-time electroholography,” Opt. Express 13, 1923–1932 (2005).
    [CrossRef]
  13. Y. Ichihashi, H. Nakayama, T. Ito, N. Masuda, T. Shimobaba, A. Shiraki, and T. Sugie, “HORN-6 special-purpose clustered computing system for electroholography,” Opt. Express 17, 13895–13903 (2009).
    [CrossRef]
  14. Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “An architecture of a high-speed digital hologram generator based on FPGA,” J. Syst. Archit. 56, 27–37 (2010).
    [CrossRef]
  15. Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “Cell-based hardware architecture for full-parallel generation algorithm of digital holograms,” Opt. Express 19, 8750–8761 (2011).
    [CrossRef]

2011 (1)

2010 (3)

2009 (2)

2006 (2)

2005 (1)

2001 (2)

H. Yoshikawa, “Fast computation of Fresnel holograms employing difference,” Opt. Rev. 8, 331–335 (2001).

T. Shimobaba and T. Ito, “An efficient computational method suitable for hardware of computer-generated hologram with phase computation by addition,” Comput. Phys. Commun. 138, 44–52 (2001).
[CrossRef]

1995 (1)

T. Motoki, H. Isono, and I. Yuyama, “Present status of three-dimensional television research,” Proc. IEEE 83, 1009–1021 (1995).
[CrossRef]

1993 (1)

M. Lucente, “Interactive computation of holograms using a look-up table,” J. Electron. Imaging 2, 28–34 (1993).
[CrossRef]

Ahrenberg, L.

Benzie, P.

Bin, R.

Chen, B.-C.

Choi, H.-J.

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “Cell-based hardware architecture for full-parallel generation algorithm of digital holograms,” Opt. Express 19, 8750–8761 (2011).
[CrossRef]

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “An architecture of a high-speed digital hologram generator based on FPGA,” J. Syst. Archit. 56, 27–37 (2010).
[CrossRef]

Chong, T.-C.

Chung, J. K.

J. K. Chung and M. H. Tsai, Three-Dimensional Holographic Imaging (Wiley, 2002).

Dong, J.-W.

Hariharan, P.

P. Hariharan, Basics of Holography (Cambridge University, 2002).

He, H.-X.

Ichihashi, Y.

Isono, H.

T. Motoki, H. Isono, and I. Yuyama, “Present status of three-dimensional television research,” Proc. IEEE 83, 1009–1021 (1995).
[CrossRef]

Ito, T.

Kim, D.-W.

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “Cell-based hardware architecture for full-parallel generation algorithm of digital holograms,” Opt. Express 19, 8750–8761 (2011).
[CrossRef]

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “An architecture of a high-speed digital hologram generator based on FPGA,” J. Syst. Archit. 56, 27–37 (2010).
[CrossRef]

Liang, X.

Liu, Y.-Z.

Lucente, M.

M. Lucente, “Interactive computation of holograms using a look-up table,” J. Electron. Imaging 2, 28–34 (1993).
[CrossRef]

Magnor, M.

Masuda, N.

Motoki, T.

T. Motoki, H. Isono, and I. Yuyama, “Present status of three-dimensional television research,” Proc. IEEE 83, 1009–1021 (1995).
[CrossRef]

Nakayama, H.

Pan, Y.

Pu, Y.-Y.

Seo, Y.-H.

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “Cell-based hardware architecture for full-parallel generation algorithm of digital holograms,” Opt. Express 19, 8750–8761 (2011).
[CrossRef]

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “An architecture of a high-speed digital hologram generator based on FPGA,” J. Syst. Archit. 56, 27–37 (2010).
[CrossRef]

Shimobaba, T.

Shiraki, A.

Solanki, S.

Sugie, T.

Takada, N.

Tan, C.

Tanaka, T.

Tanjung, A.

Tsai, M. H.

J. K. Chung and M. H. Tsai, Three-Dimensional Holographic Imaging (Wiley, 2002).

Wang, H.-Z.

Watson, J.

Xu, X.

Yoo, J.-S.

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “Cell-based hardware architecture for full-parallel generation algorithm of digital holograms,” Opt. Express 19, 8750–8761 (2011).
[CrossRef]

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “An architecture of a high-speed digital hologram generator based on FPGA,” J. Syst. Archit. 56, 27–37 (2010).
[CrossRef]

Yoshikawa, H.

H. Yoshikawa, “Fast computation of Fresnel holograms employing difference,” Opt. Rev. 8, 331–335 (2001).

Yoshimura, K.

Yuyama, I.

T. Motoki, H. Isono, and I. Yuyama, “Present status of three-dimensional television research,” Proc. IEEE 83, 1009–1021 (1995).
[CrossRef]

Comput. Phys. Commun. (1)

T. Shimobaba and T. Ito, “An efficient computational method suitable for hardware of computer-generated hologram with phase computation by addition,” Comput. Phys. Commun. 138, 44–52 (2001).
[CrossRef]

J. Electron. Imaging (1)

M. Lucente, “Interactive computation of holograms using a look-up table,” J. Electron. Imaging 2, 28–34 (1993).
[CrossRef]

J. Syst. Archit. (1)

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “An architecture of a high-speed digital hologram generator based on FPGA,” J. Syst. Archit. 56, 27–37 (2010).
[CrossRef]

Opt. Express (8)

Y.-H. Seo, H.-J. Choi, J.-S. Yoo, and D.-W. Kim, “Cell-based hardware architecture for full-parallel generation algorithm of digital holograms,” Opt. Express 19, 8750–8761 (2011).
[CrossRef]

N. Masuda, T. Ito, T. Tanaka, A. Shiraki, and T. Sugie, “Computer generated holography using a graphics processing unit,’’ Opt. Express 14, 603–608 (2006).
[CrossRef]

L. Ahrenberg, P. Benzie, M. Magnor, and J. Watson, “Computer generated holography using parallel commodity graphics hardware,” Opt. Express 14, 7636–7641 (2006).
[CrossRef]

Y. Pan, X. Xu, S. Solanki, X. Liang, R. Bin, A. Tanjung, C. Tan, and T.-C. Chong, “Fast CGH computation using S-LUT on GPU,” Opt. Express 17, 18543–18555 (2009).
[CrossRef]

Y.-Z. Liu, J.-W. Dong, Y.-Y. Pu, B.-C. Chen, H.-X. He, and H.-Z. Wang, “High-speed full analytical holographic computations for true-life scenes,” Opt. Express 18, 3345–3351 (2010).
[CrossRef]

T. Shimobaba, T. Ito, N. Masuda, Y. Ichihashi, and N. Takada, “Fast calculation of computer-generated-hologram on AMD HD5000 series GPU and OpenCL,” Opt. Express 18, 9955–9960 (2010).
[CrossRef]

T. Ito, N. Masuda, K. Yoshimura, A. Shiraki, T. Shimobaba, and T. Sugie, “Special-purpose computer HORN-5 for a real-time electroholography,” Opt. Express 13, 1923–1932 (2005).
[CrossRef]

Y. Ichihashi, H. Nakayama, T. Ito, N. Masuda, T. Shimobaba, A. Shiraki, and T. Sugie, “HORN-6 special-purpose clustered computing system for electroholography,” Opt. Express 17, 13895–13903 (2009).
[CrossRef]

Opt. Rev. (1)

H. Yoshikawa, “Fast computation of Fresnel holograms employing difference,” Opt. Rev. 8, 331–335 (2001).

Proc. IEEE (1)

T. Motoki, H. Isono, and I. Yuyama, “Present status of three-dimensional television research,” Proc. IEEE 83, 1009–1021 (1995).
[CrossRef]

Other (2)

J. K. Chung and M. H. Tsai, Three-Dimensional Holographic Imaging (Wiley, 2002).

P. Hariharan, Basics of Holography (Cambridge University, 2002).

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Figures (12)

Fig. 1.
Fig. 1.

CGH calculation schemes. (a) Light source-by-source calculation, (b) pixel-by-pixel calculation, (c) row-parallel calculation, and (d) region-parallel calculation.

Fig. 2.
Fig. 2.

Proposed hardware architecture.

Fig. 3.
Fig. 3.

Global operation sequence.

Fig. 4.
Fig. 4.

Architecture of the IIF.

Fig. 5.
Fig. 5.

Architecture of the IPC.

Fig. 6.
Fig. 6.

Architecture of the HPC.

Fig. 7.
Fig. 7.

Hardware architecture of CGH processor using IPC and HPCs.

Fig. 8.
Fig. 8.

Timing sequences of the designed hardware.

Fig. 9.
Fig. 9.

FPGA-based RTL synthesis result for an IPC.

Fig. 10.
Fig. 10.

FPGA-based RTL synthesis result for an HPC.

Fig. 11.
Fig. 11.

Part of simulation results for CGH calculation by (a) an IPC and (b) an HPC.

Fig. 12.
Fig. 12.

Experimented example images (a) at original depth and reconstructed images of DGH by (b) software and (c) proposed hardware.

Tables (3)

Tables Icon

Table 1. Bit Width for the Variable in the Proposed Hardware

Tables Icon

Table 2. Resource Utilization

Tables Icon

Table 3. Comparison of Memory Bandwidth

Equations (11)

Equations on this page are rendered with MathJax. Learn more.

Iα=jNajcos(k(pαxxαpjxxj)2+(pαyxαpjyxj)2+zj2),
Iα=jNajcos(k(zj+p22zj(xαj2+yαj2))).
Iα=jNajcos(2π(θz+θXYjd=0+Γd)),
θz(zj)=zjλ,
θXYjd=0=(p22λzj(xαj2+yαj2))d=0,
Γd(xαj,zj)=p22λzj(2dxαj+d2)=dΓ1+d(d1)Δ,
Γ1(xαj,zj)=p22λzj(2x1j+1),
Δ=p22λzj.
Γd=d[Γ1+(d1)Δ].
TCGH=Nsrc×(1+Vhologram)×Tclock,
F(x,y)=ejkzjλzejπλz(x2+y2)f(ξ,η)ejπλz(ξ2+η2)ej2πλz(ξx+ηy)dξdη.

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