Abstract

We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96.04mm2 chip using an 0.35μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2.21μs partial reconfiguration.

© 2010 Optical Society of America

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  1. Y. Pizhou and L. Chaodong, “A RISC CPU IP core,” in International Conference on Anti-Counterfeiting, Security and Identification (IEEE, 2008), pp. 356–359.
    [CrossRef]
  2. J. Goodacre and A. N. Sloss, “Parallelism and the ARM instruction set architecture,” Computer 38, 42–50 (2005).
    [CrossRef]
  3. T. Jamil, “RISC versus CISC,” IEEE Potentials 14, 13–16(1995).
    [CrossRef]
  4. D. B. Tolley, “Analysis of CISC versus RISC microprocessors for FDDI network interfaces,” in Conference on Local Computer Networks (IEEE, 1991), pp. 485–493.
  5. Altera Corporation, “Altera devices,” http://www.altera.com.
  6. Xilinx Inc., “Xilinx product data sheets,” http://www.xilinx.com.
  7. Lattice Semiconductor Corporation, “Lattice ECP and EC family data sheet” (2005), http://www.latticesemi.co.jp/products.
  8. P. Mal, P. D. Patel, and F. R. Beyette, “Design and demonstration of a fully integrated multi-technology FPGA: a reconfigurable architecture for photonic and other multi-technology applications,” IEEE Trans. Circuits Syst. I 56, 1182–1191(2009).
    [CrossRef]
  9. J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
    [CrossRef]
  10. J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24(1999).
    [CrossRef]
  11. J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” in 1999 Euro-American Workshop on Optoelectronic Information Processing, Critical Review Vol.  74 (SPIE, 1999), 265–288.
  12. M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” J. Lightwave Technol. 27, 4460–4470 (2009).
    [CrossRef]
  13. M. Nakajima and M. Watanabe, “A 100-context optically reconfigurable gate array,” in IEEE International Symposium on Circuits and Systems (IEEE, 2010), pp. 2884–2887.
  14. M. Nakajima and M. Watanabe, “36-context dynamic optically reconfigurable gate array,” in IEEE International Symposium on System Integration (IEEE, 2009), pp. 19–23.
    [CrossRef]
  15. M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515(2006).
    [CrossRef]
  16. M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Comput. Jpn. Part II 90, 132–139 (2007).
    [CrossRef]
  17. M. Watanabe, T. Shiki, and F. Kobayashi, “Scaling prospect of optically differential reconfigurable gate array VLSIs,” Analog Integr. Circ. Sig. Process. 60, 137–143, (2009).
    [CrossRef]
  18. D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
    [CrossRef]
  19. M. Watanabe and F. Kobayashi, “A logic synthesis and place and route environment for ORGAs,” in International Conference on Engineering of Reconfigurable Systems and Algorithms (2006), pp. 237–238.

2009 (3)

P. Mal, P. D. Patel, and F. R. Beyette, “Design and demonstration of a fully integrated multi-technology FPGA: a reconfigurable architecture for photonic and other multi-technology applications,” IEEE Trans. Circuits Syst. I 56, 1182–1191(2009).
[CrossRef]

M. Watanabe, T. Shiki, and F. Kobayashi, “Scaling prospect of optically differential reconfigurable gate array VLSIs,” Analog Integr. Circ. Sig. Process. 60, 137–143, (2009).
[CrossRef]

M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” J. Lightwave Technol. 27, 4460–4470 (2009).
[CrossRef]

2008 (1)

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
[CrossRef]

2007 (1)

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Comput. Jpn. Part II 90, 132–139 (2007).
[CrossRef]

2006 (1)

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515(2006).
[CrossRef]

2005 (1)

J. Goodacre and A. N. Sloss, “Parallelism and the ARM instruction set architecture,” Computer 38, 42–50 (2005).
[CrossRef]

2000 (1)

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

1999 (1)

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24(1999).
[CrossRef]

1995 (1)

T. Jamil, “RISC versus CISC,” IEEE Potentials 14, 13–16(1995).
[CrossRef]

An, X.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24(1999).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” in 1999 Euro-American Workshop on Optoelectronic Information Processing, Critical Review Vol.  74 (SPIE, 1999), 265–288.

Ay, S.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” in 1999 Euro-American Workshop on Optoelectronic Information Processing, Critical Review Vol.  74 (SPIE, 1999), 265–288.

Barna, S.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

Beyette, F. R.

P. Mal, P. D. Patel, and F. R. Beyette, “Design and demonstration of a fully integrated multi-technology FPGA: a reconfigurable architecture for photonic and other multi-technology applications,” IEEE Trans. Circuits Syst. I 56, 1182–1191(2009).
[CrossRef]

Chaodong, L.

Y. Pizhou and L. Chaodong, “A RISC CPU IP core,” in International Conference on Anti-Counterfeiting, Security and Identification (IEEE, 2008), pp. 356–359.
[CrossRef]

Corporation, Altera

Altera Corporation, “Altera devices,” http://www.altera.com.

Fossum, E.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

Goodacre, J.

J. Goodacre and A. N. Sloss, “Parallelism and the ARM instruction set architecture,” Computer 38, 42–50 (2005).
[CrossRef]

Jamil, T.

T. Jamil, “RISC versus CISC,” IEEE Potentials 14, 13–16(1995).
[CrossRef]

Kobayashi, F.

M. Watanabe, T. Shiki, and F. Kobayashi, “Scaling prospect of optically differential reconfigurable gate array VLSIs,” Analog Integr. Circ. Sig. Process. 60, 137–143, (2009).
[CrossRef]

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Comput. Jpn. Part II 90, 132–139 (2007).
[CrossRef]

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515(2006).
[CrossRef]

M. Watanabe and F. Kobayashi, “A logic synthesis and place and route environment for ORGAs,” in International Conference on Engineering of Reconfigurable Systems and Algorithms (2006), pp. 237–238.

Liu, W.

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24(1999).
[CrossRef]

Mal, P.

P. Mal, P. D. Patel, and F. R. Beyette, “Design and demonstration of a fully integrated multi-technology FPGA: a reconfigurable architecture for photonic and other multi-technology applications,” IEEE Trans. Circuits Syst. I 56, 1182–1191(2009).
[CrossRef]

Miyano, M.

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Comput. Jpn. Part II 90, 132–139 (2007).
[CrossRef]

Mok, F.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24(1999).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” in 1999 Euro-American Workshop on Optoelectronic Information Processing, Critical Review Vol.  74 (SPIE, 1999), 265–288.

Mumbru, J.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24(1999).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” in 1999 Euro-American Workshop on Optoelectronic Information Processing, Critical Review Vol.  74 (SPIE, 1999), 265–288.

Nakajima, M.

M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” J. Lightwave Technol. 27, 4460–4470 (2009).
[CrossRef]

M. Nakajima and M. Watanabe, “A 100-context optically reconfigurable gate array,” in IEEE International Symposium on Circuits and Systems (IEEE, 2010), pp. 2884–2887.

M. Nakajima and M. Watanabe, “36-context dynamic optically reconfigurable gate array,” in IEEE International Symposium on System Integration (IEEE, 2009), pp. 19–23.
[CrossRef]

Panotopoulos, G.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24(1999).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” in 1999 Euro-American Workshop on Optoelectronic Information Processing, Critical Review Vol.  74 (SPIE, 1999), 265–288.

Patel, P. D.

P. Mal, P. D. Patel, and F. R. Beyette, “Design and demonstration of a fully integrated multi-technology FPGA: a reconfigurable architecture for photonic and other multi-technology applications,” IEEE Trans. Circuits Syst. I 56, 1182–1191(2009).
[CrossRef]

Pizhou, Y.

Y. Pizhou and L. Chaodong, “A RISC CPU IP core,” in International Conference on Anti-Counterfeiting, Security and Identification (IEEE, 2008), pp. 356–359.
[CrossRef]

Psaltis, D.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24(1999).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” in 1999 Euro-American Workshop on Optoelectronic Information Processing, Critical Review Vol.  74 (SPIE, 1999), 265–288.

Seto, D.

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
[CrossRef]

Shiki, T.

M. Watanabe, T. Shiki, and F. Kobayashi, “Scaling prospect of optically differential reconfigurable gate array VLSIs,” Analog Integr. Circ. Sig. Process. 60, 137–143, (2009).
[CrossRef]

Sloss, A. N.

J. Goodacre and A. N. Sloss, “Parallelism and the ARM instruction set architecture,” Computer 38, 42–50 (2005).
[CrossRef]

Tolley, D. B.

D. B. Tolley, “Analysis of CISC versus RISC microprocessors for FDDI network interfaces,” in Conference on Local Computer Networks (IEEE, 1991), pp. 485–493.

Watanabe, M.

M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” J. Lightwave Technol. 27, 4460–4470 (2009).
[CrossRef]

M. Watanabe, T. Shiki, and F. Kobayashi, “Scaling prospect of optically differential reconfigurable gate array VLSIs,” Analog Integr. Circ. Sig. Process. 60, 137–143, (2009).
[CrossRef]

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
[CrossRef]

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Comput. Jpn. Part II 90, 132–139 (2007).
[CrossRef]

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515(2006).
[CrossRef]

M. Watanabe and F. Kobayashi, “A logic synthesis and place and route environment for ORGAs,” in International Conference on Engineering of Reconfigurable Systems and Algorithms (2006), pp. 237–238.

M. Nakajima and M. Watanabe, “36-context dynamic optically reconfigurable gate array,” in IEEE International Symposium on System Integration (IEEE, 2009), pp. 19–23.
[CrossRef]

M. Nakajima and M. Watanabe, “A 100-context optically reconfigurable gate array,” in IEEE International Symposium on Circuits and Systems (IEEE, 2010), pp. 2884–2887.

Zhou, G.

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24(1999).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” in 1999 Euro-American Workshop on Optoelectronic Information Processing, Critical Review Vol.  74 (SPIE, 1999), 265–288.

Analog Integr. Circ. Sig. Process. (1)

M. Watanabe, T. Shiki, and F. Kobayashi, “Scaling prospect of optically differential reconfigurable gate array VLSIs,” Analog Integr. Circ. Sig. Process. 60, 137–143, (2009).
[CrossRef]

Computer (1)

J. Goodacre and A. N. Sloss, “Parallelism and the ARM instruction set architecture,” Computer 38, 42–50 (2005).
[CrossRef]

Electron. Comput. Jpn. Part II (1)

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Comput. Jpn. Part II 90, 132–139 (2007).
[CrossRef]

IEEE J. Quantum Electron. (1)

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
[CrossRef]

IEEE Potentials (1)

T. Jamil, “RISC versus CISC,” IEEE Potentials 14, 13–16(1995).
[CrossRef]

IEEE Trans. Circuits Syst. I (1)

P. Mal, P. D. Patel, and F. R. Beyette, “Design and demonstration of a fully integrated multi-technology FPGA: a reconfigurable architecture for photonic and other multi-technology applications,” IEEE Trans. Circuits Syst. I 56, 1182–1191(2009).
[CrossRef]

J. Lightwave Technol. (1)

Jpn. J. Appl. Phys. (1)

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515(2006).
[CrossRef]

Proc. SPIE (2)

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24(1999).
[CrossRef]

Other (9)

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” in 1999 Euro-American Workshop on Optoelectronic Information Processing, Critical Review Vol.  74 (SPIE, 1999), 265–288.

M. Nakajima and M. Watanabe, “A 100-context optically reconfigurable gate array,” in IEEE International Symposium on Circuits and Systems (IEEE, 2010), pp. 2884–2887.

M. Nakajima and M. Watanabe, “36-context dynamic optically reconfigurable gate array,” in IEEE International Symposium on System Integration (IEEE, 2009), pp. 19–23.
[CrossRef]

D. B. Tolley, “Analysis of CISC versus RISC microprocessors for FDDI network interfaces,” in Conference on Local Computer Networks (IEEE, 1991), pp. 485–493.

Altera Corporation, “Altera devices,” http://www.altera.com.

Xilinx Inc., “Xilinx product data sheets,” http://www.xilinx.com.

Lattice Semiconductor Corporation, “Lattice ECP and EC family data sheet” (2005), http://www.latticesemi.co.jp/products.

Y. Pizhou and L. Chaodong, “A RISC CPU IP core,” in International Conference on Anti-Counterfeiting, Security and Identification (IEEE, 2008), pp. 356–359.
[CrossRef]

M. Watanabe and F. Kobayashi, “A logic synthesis and place and route environment for ORGAs,” in International Conference on Engineering of Reconfigurable Systems and Algorithms (2006), pp. 237–238.

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Figures (13)

Fig. 1
Fig. 1

Optical reconfiguration circuits including a partial block-by-block reconfiguration indication circuit.

Fig. 2
Fig. 2

Timing diagram of a partial reconfiguration.

Fig. 3
Fig. 3

11,424 gate-count DORGA-VLSI chip using a 0.35 μm , 9.8 mm 2 CMOS process chip, and its board including the chip.

Fig. 4
Fig. 4

Block diagram and CAD layout of an ORLB.

Fig. 5
Fig. 5

Block diagram and CAD layout of an ORSM.

Fig. 6
Fig. 6

Holographic memory calculation tool.

Fig. 7
Fig. 7

Alignment adjustment tool.

Fig. 8
Fig. 8

Estimation system.

Fig. 9
Fig. 9

(a) Holographic memory pattern and (b) CCD image of a configuration context of an AND circuit.

Fig. 10
Fig. 10

Experimental system, which is the same as the previous system except for the inclusion of a laser source. (a) Photograph of the DORGA holographic reconfiguration architecture. (b) Expanded photograph of the area around the DORGA-VLSI.

Fig. 11
Fig. 11

(a) Holographic memory pattern and (b) CCD-captured image of a configuration context of a NOR circuit.

Fig. 12
Fig. 12

Implementation of a three-stage ring oscillator. (a) Block diagram, (b) a holographic memory pattern, (c) a CCD-captured configuration context, and (d) a waveform of the three-stage ring oscillator.

Fig. 13
Fig. 13

(a) Holographic memory pattern and (b) CCD-captured image of a configuration context of a full-adder circuit.

Tables (1)

Tables Icon

Table 1 DORGA-VLSI Specifications

Equations (3)

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H ( x 1 , y 1 ) - - O ( x 2 , y 2 ) sin ( k r ) d x 2 d y 2 , r = Z L 2 + ( x 1 - x 2 ) 2 + ( y 1 - y 2 ) 2 ,
H ( x 1 , y 1 ) = H ( x 1 , y 1 ) - H m i n H m a x - H m i n .
P a l l = P o p t + P c o n f + P g a t e ,

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