Abstract

This paper proposes a method of superimposing acceleration and optimizing the optical reconfiguration speed while requiring no increase of laser power. Using this technique, the optical reconfiguration speed is increased by superimposing multiple configuration contexts. Simultaneously, optimization of the number of configuration contexts and reconfiguration speed is possible. A full four-context optically reconfigurable gate array system consisting of an optically reconfigurable gate array VLSI, an easily rewritable liquid crystal holographic memory, and four vertical-cavity surface-emitting lasers was constructed to demonstrate this method. This paper clarifies the method’s benefits using experimental results obtained from the demonstration system.

© 2010 Optical Society of America

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References

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  1. Intel Corporation, “Processors,” http://www.intel.com.
  2. Altera Corporation, “Altera devices,” http://www.altera.com.
  3. Xilinx Inc., “Xilinx product data sheets,” http://www.xilinx.com.
  4. Lattice Semiconductor Corporation, “LatticeECP and EC family data sheet,” http://www.latticesemi.co.jp/products (2005).
  5. J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
    [CrossRef]
  6. J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24 (1999).
    [CrossRef]
  7. J. Mumbru, G. Panotopulos, Z. Gan, A. Xin, and M. Fai, “Optically reconfigurable processors,” in Southwest Symposium on Mixed-Signal Design (IEEE, 2000), p. 22.
    [CrossRef]
  8. M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515 (2006).
    [CrossRef]
  9. D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
    [CrossRef]
  10. M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” J. Lightwave Technol. 274460–4470 (2009).
    [CrossRef]
  11. Fuji Xerox Co., Ltd., “VCSEL-ROS,” http://www.fujixerox.com/eng/.
  12. N. Yamaguchi and M. Watanabe, “Liquid crystal holographic configurations for ORGAs,” Appl. Opt. 47, 4692–4700 (2008).
    [CrossRef] [PubMed]

2009 (1)

2008 (2)

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
[CrossRef]

N. Yamaguchi and M. Watanabe, “Liquid crystal holographic configurations for ORGAs,” Appl. Opt. 47, 4692–4700 (2008).
[CrossRef] [PubMed]

2006 (1)

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515 (2006).
[CrossRef]

2000 (1)

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

1999 (1)

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24 (1999).
[CrossRef]

An, X.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24 (1999).
[CrossRef]

Ay, S.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

Barna, S.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

Fai, M.

J. Mumbru, G. Panotopulos, Z. Gan, A. Xin, and M. Fai, “Optically reconfigurable processors,” in Southwest Symposium on Mixed-Signal Design (IEEE, 2000), p. 22.
[CrossRef]

Fossum, E.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

Gan, Z.

J. Mumbru, G. Panotopulos, Z. Gan, A. Xin, and M. Fai, “Optically reconfigurable processors,” in Southwest Symposium on Mixed-Signal Design (IEEE, 2000), p. 22.
[CrossRef]

Kobayashi, F.

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515 (2006).
[CrossRef]

Liu, W.

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24 (1999).
[CrossRef]

Mok, F.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24 (1999).
[CrossRef]

Mumbru, J.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24 (1999).
[CrossRef]

J. Mumbru, G. Panotopulos, Z. Gan, A. Xin, and M. Fai, “Optically reconfigurable processors,” in Southwest Symposium on Mixed-Signal Design (IEEE, 2000), p. 22.
[CrossRef]

Nakajima, M.

Panotopoulos, G.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24 (1999).
[CrossRef]

Panotopulos, G.

J. Mumbru, G. Panotopulos, Z. Gan, A. Xin, and M. Fai, “Optically reconfigurable processors,” in Southwest Symposium on Mixed-Signal Design (IEEE, 2000), p. 22.
[CrossRef]

Psaltis, D.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24 (1999).
[CrossRef]

Seto, D.

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
[CrossRef]

Watanabe, M.

M. Nakajima and M. Watanabe, “A four-context optically differential reconfigurable gate array,” J. Lightwave Technol. 274460–4470 (2009).
[CrossRef]

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
[CrossRef]

N. Yamaguchi and M. Watanabe, “Liquid crystal holographic configurations for ORGAs,” Appl. Opt. 47, 4692–4700 (2008).
[CrossRef] [PubMed]

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515 (2006).
[CrossRef]

Xin, A.

J. Mumbru, G. Panotopulos, Z. Gan, A. Xin, and M. Fai, “Optically reconfigurable processors,” in Southwest Symposium on Mixed-Signal Design (IEEE, 2000), p. 22.
[CrossRef]

Yamaguchi, N.

Zhou, G.

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24 (1999).
[CrossRef]

Appl. Opt. (1)

IEEE J. Quantum Electron. (1)

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array—perfect emulation,” IEEE J. Quantum Electron. 44, 493–500 (2008).
[CrossRef]

J. Lightwave Technol. (1)

Jpn. J. Appl. Phys. (1)

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510–3515 (2006).
[CrossRef]

Proc. SPIE (2)

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763–771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14–24 (1999).
[CrossRef]

Other (6)

J. Mumbru, G. Panotopulos, Z. Gan, A. Xin, and M. Fai, “Optically reconfigurable processors,” in Southwest Symposium on Mixed-Signal Design (IEEE, 2000), p. 22.
[CrossRef]

Fuji Xerox Co., Ltd., “VCSEL-ROS,” http://www.fujixerox.com/eng/.

Intel Corporation, “Processors,” http://www.intel.com.

Altera Corporation, “Altera devices,” http://www.altera.com.

Xilinx Inc., “Xilinx product data sheets,” http://www.xilinx.com.

Lattice Semiconductor Corporation, “LatticeECP and EC family data sheet,” http://www.latticesemi.co.jp/products (2005).

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Figures (13)

Fig. 1
Fig. 1

ORGA block diagram.

Fig. 2
Fig. 2

Experimental system.

Fig. 3
Fig. 3

Holographic memory patterns—displayed on an LC-SLM—used for generating four-configuration context patterns for an ORGA-VLSI. The holographic memory patterns are those for (a) an AND circuit, (b) a NAND circuit, (c) a majority voting circuit, and (d) a half-adder circuit. All four areas in each the holographic memory include the same circuit information.

Fig. 4
Fig. 4

Sample configuration contexts of an AND circuit, a NAND circuit, a majority voting circuit, and a half-adder circuit.

Fig. 5
Fig. 5

CCD-captured single-configuration-context patterns of an AND circuit, a NAND circuit, a majority voting circuit, and a half-adder circuit.

Fig. 6
Fig. 6

Waveform of an AND circuit configuration.

Fig. 7
Fig. 7

Waveform of a NAND circuit configuration.

Fig. 8
Fig. 8

Waveform of a majority voting circuit configuration.

Fig. 9
Fig. 9

Waveform of a half-adder circuit configuration.

Fig. 10
Fig. 10

Block diagram of a reconfiguration method of conventional ORGAs. One context was read out by turning on a laser diode.

Fig. 11
Fig. 11

Block diagram of a superimposing reconfiguration technique. This technique enables multiple laser diodes to be turned on when a context is programmed on an ORGA-VLSI.

Fig. 12
Fig. 12

CCD captured images of a two-context superimposing configuration pattern, a three-context superimposing configuration pattern, and a four-context superimposing configuration pattern of an AND circuit.

Fig. 13
Fig. 13

Relation between the reconfiguration period and number of superimposing configuration contexts for each circuit.

Tables (1)

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Table 1 ORGA-VLSI Specifications

Equations (2)

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H ( x 1 , y 1 ) O ( x 2 , y 2 ) sin ( k r ) d x 2 d y 2 , r = Z L 2 + ( x 1 x 2 ) 2 + ( y 1 y 2 ) 2 + Z Laser 2 + ( x Laser x 1 ) 2 + ( y Laser y 1 ) 2 .
H ( x 1 , y 1 ) = H ( x 1 , y 1 ) H min H max H min .

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