Abstract

Applying the parallelism of optical computing, we present a novel method of vector-matrix multiplication (VMM) based on a new optical computing platform, the ternary optical computer, which can reconfigure any two-input trivalued logic optical processor at runtime, according to the decrease-radix design principle. In this work, we investigate a novel optical VMM (OVMM) using five logic operations with the modified signed-digit (MSD) number system. To simplify the computation process, we realize a carry-free optical addition in three steps, which is independent of the length of the operands. And a new implementation method is proposed that can be used to realize the MSD multiplication in parallel. Based on the generation of partial products in parallel and the binary-addition-tree algorithm, the multiplication can be implemented with the MSD addition. Our initial experiments have been performed to verify the proposed OVMM method. The results show that the proposed method of OVMM is feasible and correct.

© 2010 Optical Society of America

Full Article  |  PDF Article

References

  • View by:
  • |
  • |
  • |

  1. R. A. Heinz, J. O. Artman, and S. H. Lee, “Matrix multiplication by optical methods,” Appl. Opt.  9, 2161–2168 (1970).
    [CrossRef] [PubMed]
  2. E. P. Mosca, R. D. Griffin, F. P. Pursel, and J. N. Lee, “Acoustooptical matrix-vector product processor: implementation issues,” Appl. Opt.  28, 3843–3851 (1989).
    [CrossRef] [PubMed]
  3. S. A. Ellett, J. F. Walkup, and T. F. Krile, “Error-correction coding for accuracy enhancement in optical matrix-vector multipliers,” Appl. Opt.  31, 5642–5653 (1992).
    [CrossRef] [PubMed]
  4. N. Q. Ngo and L. N. Binh, “Fiber-optic array algebraic processing architectures,” Appl. Opt.  34, 803–815 (1995).
    [CrossRef] [PubMed]
  5. A. P. Goutzoulis, “Systolic time-integrating acousto-optic binary processor,” Appl. Opt.  23, 4095–4099 (1984).
    [CrossRef] [PubMed]
  6. E. J. Baranoski and D. P. Casasent, “High-accuracy optical processors: a new performance comparison,” Appl. Opt.  28, 5351–5357 (1989).
    [CrossRef] [PubMed]
  7. J. W. Goodman, A. R. Dias, and L. M. Woody, “Fully parallel, high-speed incoherent optical method for performing discrete Fourier transforms,” Opt. Lett.  2, 1–3 (1978).
    [CrossRef] [PubMed]
  8. K. Al-Ghoneim and D. Casasent, “High-accuracy pipelined iterative-tree optical multiplication,” Appl. Opt.  33, 1517–1527 (1994).
    [CrossRef] [PubMed]
  9. C. K. Gary, “Matrix-vector multiplication using digital partitioning for more accurate optical computing,” Appl. Opt.  31, 6205–6211 (1992).
    [CrossRef] [PubMed]
  10. S. A. Ellett, T. F. Krile, and J. F. Walkup, “Throughput analysis of digital partitioning with error-correcting codes for optical matrix-vector processors,” Appl. Opt.  34, 6744–6751 (1995).
    [CrossRef] [PubMed]
  11. M. Li, H. C. He, and Y. Jin, “A new method for optical vector-matrix multiplier,” in Proceedings of 2009 International Conference on Electronic Computer Technology (Computer Society Press, 2009), pp. 191–194.
    [CrossRef]
  12. D. Casasent and B. K. Taylor, “Banded-matrix high-performance algorithm and architecture,” Appl. Opt.  24, 1476–1480 (1985).
    [CrossRef] [PubMed]
  13. R. P. Bocker, S. R. Clayton, and K. Bromley, “Electrooptical matrix multiplication using the twos complement arithmetic for improved accuracy,” Appl. Opt.  22, 2019–2021 (1983).
    [CrossRef] [PubMed]
  14. M. Hűbner and J. Becker, “Exploiting dynamic and partial reconfiguration for FPGAs-toolflow, architecture, and system integration,” in Proceedings of the 19th SBCCI Symposium on Integrated Circuits and Systems Design (ACM, 2006), pp. 1–4.
  15. R. Hymel, A. D. George, and H. LAM, “Evaluating partial reconfiguration for embedded FPGA applications,” in Proceedings of High-Performance Embedded Computing Workshop (HPEC’07) (IEEE, 2007), pp. 1–2.
  16. V. Aggarwal, A. D. George, and K. C. Slatton, “Reconfigurable computing with multiscale data fusion for remote sensing,” in Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays (FPGA’06) (ACM, 2006), p. 235.
  17. E. El-ArabyI. Gonzalez, and T. El-Ghazawi, “Exploiting partial runtime reconfiguration for high-performance reconfigurable computing,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2009).
    [CrossRef]
  18. D. B. Thomas and W. Luk, “Multivariate Gaussian random number generation targeting reconfigurable hardware,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
    [CrossRef]
  19. S.-L. L. Lu, P. Yiannacouras, T. Suh, R. Kassa, and M. Konow, “A desktop computer with a reconfigurable Pentium,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
    [CrossRef]
  20. J. S. Beeckler and W. J. Gross, “Particle graphics on reconfigurable hardware,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
    [CrossRef]
  21. A. Huang, Y. Tsunoda, J. W. Goodman, and S. Ishihara, “Optical computation using residue arithmetic,” Appl. Opt.  18, 149–162 (1979).
    [CrossRef] [PubMed]
  22. A. Avizienis, “Signed-digit number representations for fast parallel arithmetic,” IRE Trans. Electron. Comp.  EC-10, 389–400 (1961).
    [CrossRef]
  23. R. A. Athale, “Highly redundant number representation for medium accuracy optical computing,” Appl. Opt.  25, 3122–3127 (1986).
    [CrossRef] [PubMed]
  24. A. K. Cherri and M. S. Alam, “Recoded and nonrecoded trinary signed-digit adders and multipliers with redundant-bit representations,” Appl. Opt.  37, 4405–4418(1998).
    [CrossRef]
  25. R. P. Bocker, B. L. Drake, M. E. Lasher, and T. B. Henderson, “Modified signed-digit addition and subtraction using optical symbolic substitution,” Appl. Opt.  25, 2456–2457 (1986).
    [CrossRef] [PubMed]
  26. Y. Jin, H. C. He, and Y. T. Lű, “Ternary optical computer principle,” Sci. China Ser. F  46, 145–150 (2003).
    [CrossRef]
  27. Y. Jin, H. C. He, and Y. T. Lű, “Ternary optical computer architecture,” Phys. Scr.  59, 98–101 (2005).
    [CrossRef]
  28. Z. Y. Shen, Y. Jin, and J. J. Peng, “Experimental system of ternary logic optical computer with reconfigurability,” Proc. SPIE  7282, 72823I (2009).
    [CrossRef]
  29. J. Y. Yan, Y. Jin, and K. Z. Zuo, “Decrease-radix design principle for carrying/borrowing free multi-valued and application in ternary optical computer,” Sci. China Ser. F  51, 1415–1426 (2008).
    [CrossRef]
  30. J. E. Robertson, “A deterministic procedure for the design of carry-save adders and borrow-save subtractors,” University of Illinois, Urbana-Champaign, Department of Computer Science Report no. 235 (1967).
  31. H. Ling, “High speed binary adder,” IBM J. Res. Develop.  25, 156–166 (1981).
    [CrossRef]
  32. N. Takagi, H. Yasuura, and S. Yajima, “High-speed VLSI multiplication algorithm with a redundant binary addition tree,” IEEE Trans. Comput.  C-34, 789–796 (1985).
    [CrossRef]
  33. M. M. Mirsalehi and T. K. Gaylord, “Logical minimization of multilevel coded functions,” Appl. Opt.  25, 3078–3088 (1986).
    [CrossRef] [PubMed]

2009

E. El-ArabyI. Gonzalez, and T. El-Ghazawi, “Exploiting partial runtime reconfiguration for high-performance reconfigurable computing,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2009).
[CrossRef]

Z. Y. Shen, Y. Jin, and J. J. Peng, “Experimental system of ternary logic optical computer with reconfigurability,” Proc. SPIE  7282, 72823I (2009).
[CrossRef]

2008

J. Y. Yan, Y. Jin, and K. Z. Zuo, “Decrease-radix design principle for carrying/borrowing free multi-valued and application in ternary optical computer,” Sci. China Ser. F  51, 1415–1426 (2008).
[CrossRef]

D. B. Thomas and W. Luk, “Multivariate Gaussian random number generation targeting reconfigurable hardware,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

S.-L. L. Lu, P. Yiannacouras, T. Suh, R. Kassa, and M. Konow, “A desktop computer with a reconfigurable Pentium,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

J. S. Beeckler and W. J. Gross, “Particle graphics on reconfigurable hardware,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

2005

Y. Jin, H. C. He, and Y. T. Lű, “Ternary optical computer architecture,” Phys. Scr.  59, 98–101 (2005).
[CrossRef]

2003

Y. Jin, H. C. He, and Y. T. Lű, “Ternary optical computer principle,” Sci. China Ser. F  46, 145–150 (2003).
[CrossRef]

1998

1995

1994

1992

1989

1986

1985

D. Casasent and B. K. Taylor, “Banded-matrix high-performance algorithm and architecture,” Appl. Opt.  24, 1476–1480 (1985).
[CrossRef] [PubMed]

N. Takagi, H. Yasuura, and S. Yajima, “High-speed VLSI multiplication algorithm with a redundant binary addition tree,” IEEE Trans. Comput.  C-34, 789–796 (1985).
[CrossRef]

1984

1983

1981

H. Ling, “High speed binary adder,” IBM J. Res. Develop.  25, 156–166 (1981).
[CrossRef]

1979

1978

1970

1961

A. Avizienis, “Signed-digit number representations for fast parallel arithmetic,” IRE Trans. Electron. Comp.  EC-10, 389–400 (1961).
[CrossRef]

Aggarwal, V.

V. Aggarwal, A. D. George, and K. C. Slatton, “Reconfigurable computing with multiscale data fusion for remote sensing,” in Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays (FPGA’06) (ACM, 2006), p. 235.

Alam, M. S.

Al-Ghoneim, K.

Artman, J. O.

Athale, R. A.

Avizienis, A.

A. Avizienis, “Signed-digit number representations for fast parallel arithmetic,” IRE Trans. Electron. Comp.  EC-10, 389–400 (1961).
[CrossRef]

Baranoski, E. J.

Becker, J.

M. Hűbner and J. Becker, “Exploiting dynamic and partial reconfiguration for FPGAs-toolflow, architecture, and system integration,” in Proceedings of the 19th SBCCI Symposium on Integrated Circuits and Systems Design (ACM, 2006), pp. 1–4.

Beeckler, J. S.

J. S. Beeckler and W. J. Gross, “Particle graphics on reconfigurable hardware,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

Binh, L. N.

Bocker, R. P.

Bromley, K.

Casasent, D.

Casasent, D. P.

Cherri, A. K.

Clayton, S. R.

Dias, A. R.

Drake, B. L.

El-Araby, E.

E. El-ArabyI. Gonzalez, and T. El-Ghazawi, “Exploiting partial runtime reconfiguration for high-performance reconfigurable computing,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2009).
[CrossRef]

El-Ghazawi, T.

E. El-ArabyI. Gonzalez, and T. El-Ghazawi, “Exploiting partial runtime reconfiguration for high-performance reconfigurable computing,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2009).
[CrossRef]

Ellett, S. A.

Gary, C. K.

Gaylord, T. K.

George, A. D.

V. Aggarwal, A. D. George, and K. C. Slatton, “Reconfigurable computing with multiscale data fusion for remote sensing,” in Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays (FPGA’06) (ACM, 2006), p. 235.

R. Hymel, A. D. George, and H. LAM, “Evaluating partial reconfiguration for embedded FPGA applications,” in Proceedings of High-Performance Embedded Computing Workshop (HPEC’07) (IEEE, 2007), pp. 1–2.

Gonzalez, I.

E. El-ArabyI. Gonzalez, and T. El-Ghazawi, “Exploiting partial runtime reconfiguration for high-performance reconfigurable computing,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2009).
[CrossRef]

Goodman, J. W.

Goutzoulis, A. P.

Griffin, R. D.

Gross, W. J.

J. S. Beeckler and W. J. Gross, “Particle graphics on reconfigurable hardware,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

He, H. C.

Y. Jin, H. C. He, and Y. T. Lű, “Ternary optical computer architecture,” Phys. Scr.  59, 98–101 (2005).
[CrossRef]

Y. Jin, H. C. He, and Y. T. Lű, “Ternary optical computer principle,” Sci. China Ser. F  46, 145–150 (2003).
[CrossRef]

M. Li, H. C. He, and Y. Jin, “A new method for optical vector-matrix multiplier,” in Proceedings of 2009 International Conference on Electronic Computer Technology (Computer Society Press, 2009), pp. 191–194.
[CrossRef]

Heinz, R. A.

Henderson, T. B.

Huang, A.

Hubner, M.

M. Hűbner and J. Becker, “Exploiting dynamic and partial reconfiguration for FPGAs-toolflow, architecture, and system integration,” in Proceedings of the 19th SBCCI Symposium on Integrated Circuits and Systems Design (ACM, 2006), pp. 1–4.

Hymel, R.

R. Hymel, A. D. George, and H. LAM, “Evaluating partial reconfiguration for embedded FPGA applications,” in Proceedings of High-Performance Embedded Computing Workshop (HPEC’07) (IEEE, 2007), pp. 1–2.

Ishihara, S.

Jin, Y.

Z. Y. Shen, Y. Jin, and J. J. Peng, “Experimental system of ternary logic optical computer with reconfigurability,” Proc. SPIE  7282, 72823I (2009).
[CrossRef]

J. Y. Yan, Y. Jin, and K. Z. Zuo, “Decrease-radix design principle for carrying/borrowing free multi-valued and application in ternary optical computer,” Sci. China Ser. F  51, 1415–1426 (2008).
[CrossRef]

Y. Jin, H. C. He, and Y. T. Lű, “Ternary optical computer architecture,” Phys. Scr.  59, 98–101 (2005).
[CrossRef]

Y. Jin, H. C. He, and Y. T. Lű, “Ternary optical computer principle,” Sci. China Ser. F  46, 145–150 (2003).
[CrossRef]

M. Li, H. C. He, and Y. Jin, “A new method for optical vector-matrix multiplier,” in Proceedings of 2009 International Conference on Electronic Computer Technology (Computer Society Press, 2009), pp. 191–194.
[CrossRef]

Kassa, R.

S.-L. L. Lu, P. Yiannacouras, T. Suh, R. Kassa, and M. Konow, “A desktop computer with a reconfigurable Pentium,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

Konow, M.

S.-L. L. Lu, P. Yiannacouras, T. Suh, R. Kassa, and M. Konow, “A desktop computer with a reconfigurable Pentium,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

Krile, T. F.

LAM, H.

R. Hymel, A. D. George, and H. LAM, “Evaluating partial reconfiguration for embedded FPGA applications,” in Proceedings of High-Performance Embedded Computing Workshop (HPEC’07) (IEEE, 2007), pp. 1–2.

Lasher, M. E.

Lee, J. N.

Lee, S. H.

Li, M.

M. Li, H. C. He, and Y. Jin, “A new method for optical vector-matrix multiplier,” in Proceedings of 2009 International Conference on Electronic Computer Technology (Computer Society Press, 2009), pp. 191–194.
[CrossRef]

Ling, H.

H. Ling, “High speed binary adder,” IBM J. Res. Develop.  25, 156–166 (1981).
[CrossRef]

Lu, S.-L. L.

S.-L. L. Lu, P. Yiannacouras, T. Suh, R. Kassa, and M. Konow, “A desktop computer with a reconfigurable Pentium,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

Lu, Y. T.

Y. Jin, H. C. He, and Y. T. Lű, “Ternary optical computer architecture,” Phys. Scr.  59, 98–101 (2005).
[CrossRef]

Y. Jin, H. C. He, and Y. T. Lű, “Ternary optical computer principle,” Sci. China Ser. F  46, 145–150 (2003).
[CrossRef]

Luk, W.

D. B. Thomas and W. Luk, “Multivariate Gaussian random number generation targeting reconfigurable hardware,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

Mirsalehi, M. M.

Mosca, E. P.

Ngo, N. Q.

Peng, J. J.

Z. Y. Shen, Y. Jin, and J. J. Peng, “Experimental system of ternary logic optical computer with reconfigurability,” Proc. SPIE  7282, 72823I (2009).
[CrossRef]

Pursel, F. P.

Robertson, J. E.

J. E. Robertson, “A deterministic procedure for the design of carry-save adders and borrow-save subtractors,” University of Illinois, Urbana-Champaign, Department of Computer Science Report no. 235 (1967).

Shen, Z. Y.

Z. Y. Shen, Y. Jin, and J. J. Peng, “Experimental system of ternary logic optical computer with reconfigurability,” Proc. SPIE  7282, 72823I (2009).
[CrossRef]

Slatton, K. C.

V. Aggarwal, A. D. George, and K. C. Slatton, “Reconfigurable computing with multiscale data fusion for remote sensing,” in Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays (FPGA’06) (ACM, 2006), p. 235.

Suh, T.

S.-L. L. Lu, P. Yiannacouras, T. Suh, R. Kassa, and M. Konow, “A desktop computer with a reconfigurable Pentium,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

Takagi, N.

N. Takagi, H. Yasuura, and S. Yajima, “High-speed VLSI multiplication algorithm with a redundant binary addition tree,” IEEE Trans. Comput.  C-34, 789–796 (1985).
[CrossRef]

Taylor, B. K.

Thomas, D. B.

D. B. Thomas and W. Luk, “Multivariate Gaussian random number generation targeting reconfigurable hardware,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

Tsunoda, Y.

Walkup, J. F.

Woody, L. M.

Yajima, S.

N. Takagi, H. Yasuura, and S. Yajima, “High-speed VLSI multiplication algorithm with a redundant binary addition tree,” IEEE Trans. Comput.  C-34, 789–796 (1985).
[CrossRef]

Yan, J. Y.

J. Y. Yan, Y. Jin, and K. Z. Zuo, “Decrease-radix design principle for carrying/borrowing free multi-valued and application in ternary optical computer,” Sci. China Ser. F  51, 1415–1426 (2008).
[CrossRef]

Yasuura, H.

N. Takagi, H. Yasuura, and S. Yajima, “High-speed VLSI multiplication algorithm with a redundant binary addition tree,” IEEE Trans. Comput.  C-34, 789–796 (1985).
[CrossRef]

Yiannacouras, P.

S.-L. L. Lu, P. Yiannacouras, T. Suh, R. Kassa, and M. Konow, “A desktop computer with a reconfigurable Pentium,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

Zuo, K. Z.

J. Y. Yan, Y. Jin, and K. Z. Zuo, “Decrease-radix design principle for carrying/borrowing free multi-valued and application in ternary optical computer,” Sci. China Ser. F  51, 1415–1426 (2008).
[CrossRef]

ACM Trans. Reconfig. Techn. Syst.

E. El-ArabyI. Gonzalez, and T. El-Ghazawi, “Exploiting partial runtime reconfiguration for high-performance reconfigurable computing,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2009).
[CrossRef]

D. B. Thomas and W. Luk, “Multivariate Gaussian random number generation targeting reconfigurable hardware,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

S.-L. L. Lu, P. Yiannacouras, T. Suh, R. Kassa, and M. Konow, “A desktop computer with a reconfigurable Pentium,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

J. S. Beeckler and W. J. Gross, “Particle graphics on reconfigurable hardware,” ACM Trans. Reconfig. Techn. Syst.  1, 1 (2008).
[CrossRef]

Appl. Opt.

R. A. Heinz, J. O. Artman, and S. H. Lee, “Matrix multiplication by optical methods,” Appl. Opt.  9, 2161–2168 (1970).
[CrossRef] [PubMed]

A. Huang, Y. Tsunoda, J. W. Goodman, and S. Ishihara, “Optical computation using residue arithmetic,” Appl. Opt.  18, 149–162 (1979).
[CrossRef] [PubMed]

R. P. Bocker, S. R. Clayton, and K. Bromley, “Electrooptical matrix multiplication using the twos complement arithmetic for improved accuracy,” Appl. Opt.  22, 2019–2021 (1983).
[CrossRef] [PubMed]

A. P. Goutzoulis, “Systolic time-integrating acousto-optic binary processor,” Appl. Opt.  23, 4095–4099 (1984).
[CrossRef] [PubMed]

D. Casasent and B. K. Taylor, “Banded-matrix high-performance algorithm and architecture,” Appl. Opt.  24, 1476–1480 (1985).
[CrossRef] [PubMed]

R. P. Bocker, B. L. Drake, M. E. Lasher, and T. B. Henderson, “Modified signed-digit addition and subtraction using optical symbolic substitution,” Appl. Opt.  25, 2456–2457 (1986).
[CrossRef] [PubMed]

M. M. Mirsalehi and T. K. Gaylord, “Logical minimization of multilevel coded functions,” Appl. Opt.  25, 3078–3088 (1986).
[CrossRef] [PubMed]

R. A. Athale, “Highly redundant number representation for medium accuracy optical computing,” Appl. Opt.  25, 3122–3127 (1986).
[CrossRef] [PubMed]

E. P. Mosca, R. D. Griffin, F. P. Pursel, and J. N. Lee, “Acoustooptical matrix-vector product processor: implementation issues,” Appl. Opt.  28, 3843–3851 (1989).
[CrossRef] [PubMed]

E. J. Baranoski and D. P. Casasent, “High-accuracy optical processors: a new performance comparison,” Appl. Opt.  28, 5351–5357 (1989).
[CrossRef] [PubMed]

S. A. Ellett, J. F. Walkup, and T. F. Krile, “Error-correction coding for accuracy enhancement in optical matrix-vector multipliers,” Appl. Opt.  31, 5642–5653 (1992).
[CrossRef] [PubMed]

K. Al-Ghoneim and D. Casasent, “High-accuracy pipelined iterative-tree optical multiplication,” Appl. Opt.  33, 1517–1527 (1994).
[CrossRef] [PubMed]

A. K. Cherri and M. S. Alam, “Recoded and nonrecoded trinary signed-digit adders and multipliers with redundant-bit representations,” Appl. Opt.  37, 4405–4418(1998).
[CrossRef]

N. Q. Ngo and L. N. Binh, “Fiber-optic array algebraic processing architectures,” Appl. Opt.  34, 803–815 (1995).
[CrossRef] [PubMed]

S. A. Ellett, T. F. Krile, and J. F. Walkup, “Throughput analysis of digital partitioning with error-correcting codes for optical matrix-vector processors,” Appl. Opt.  34, 6744–6751 (1995).
[CrossRef] [PubMed]

C. K. Gary, “Matrix-vector multiplication using digital partitioning for more accurate optical computing,” Appl. Opt.  31, 6205–6211 (1992).
[CrossRef] [PubMed]

IBM J. Res. Develop.

H. Ling, “High speed binary adder,” IBM J. Res. Develop.  25, 156–166 (1981).
[CrossRef]

IEEE Trans. Comput.

N. Takagi, H. Yasuura, and S. Yajima, “High-speed VLSI multiplication algorithm with a redundant binary addition tree,” IEEE Trans. Comput.  C-34, 789–796 (1985).
[CrossRef]

IRE Trans. Electron. Comp.

A. Avizienis, “Signed-digit number representations for fast parallel arithmetic,” IRE Trans. Electron. Comp.  EC-10, 389–400 (1961).
[CrossRef]

Opt. Lett.

Phys. Scr.

Y. Jin, H. C. He, and Y. T. Lű, “Ternary optical computer architecture,” Phys. Scr.  59, 98–101 (2005).
[CrossRef]

Proc. SPIE

Z. Y. Shen, Y. Jin, and J. J. Peng, “Experimental system of ternary logic optical computer with reconfigurability,” Proc. SPIE  7282, 72823I (2009).
[CrossRef]

Sci. China Ser. F

J. Y. Yan, Y. Jin, and K. Z. Zuo, “Decrease-radix design principle for carrying/borrowing free multi-valued and application in ternary optical computer,” Sci. China Ser. F  51, 1415–1426 (2008).
[CrossRef]

Y. Jin, H. C. He, and Y. T. Lű, “Ternary optical computer principle,” Sci. China Ser. F  46, 145–150 (2003).
[CrossRef]

Other

J. E. Robertson, “A deterministic procedure for the design of carry-save adders and borrow-save subtractors,” University of Illinois, Urbana-Champaign, Department of Computer Science Report no. 235 (1967).

M. Li, H. C. He, and Y. Jin, “A new method for optical vector-matrix multiplier,” in Proceedings of 2009 International Conference on Electronic Computer Technology (Computer Society Press, 2009), pp. 191–194.
[CrossRef]

M. Hűbner and J. Becker, “Exploiting dynamic and partial reconfiguration for FPGAs-toolflow, architecture, and system integration,” in Proceedings of the 19th SBCCI Symposium on Integrated Circuits and Systems Design (ACM, 2006), pp. 1–4.

R. Hymel, A. D. George, and H. LAM, “Evaluating partial reconfiguration for embedded FPGA applications,” in Proceedings of High-Performance Embedded Computing Workshop (HPEC’07) (IEEE, 2007), pp. 1–2.

V. Aggarwal, A. D. George, and K. C. Slatton, “Reconfigurable computing with multiscale data fusion for remote sensing,” in Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays (FPGA’06) (ACM, 2006), p. 235.

Cited By

OSA participates in CrossRef's Cited-By Linking service. Citing articles from OSA journals and other participating publishers are listed here.

Alert me when this article is cited.


Figures (7)

Fig. 1
Fig. 1

Architecture of the optical part of the TOC.

Fig. 2
Fig. 2

Flow of MSD addition.

Fig. 3
Fig. 3

Example of multiplication of two four-bit MSD numbers.

Fig. 4
Fig. 4

Schematic flow of VMM by the BATA.

Fig. 5
Fig. 5

Efficiency of the BATA.

Fig. 6
Fig. 6

Outputs of (a) step 1, (b) step 2, (c) step 3, and (d) step 4, which are used to compute the products of relevant elements. Theoretically, the operation results can be obtained by judging whether the BOUs are bright, but, in fact, there are several different intensity levels in each part because of the limitations of experimental conditions. For the same reason, BOUs may have several intensity levels, and only those greater than a given intensity level threshold serve as LPBOUs. All the LPBOUs have been marked in broken-line boxes. This rule is also suitable for Fig. 7.

Fig. 7
Fig. 7

Outputs of (a) step 5, (b) step 6, and (c) step 7, which are used to compute the VIPs of the products from step 4.

Tables (3)

Tables Icon

Table 1 Truth Tables for T, W, T , W , and M Transformations

Tables Icon

Table 2 Process of Modified Signed-Digit Addition

Tables Icon

Table 3 Information on Transformations Implemented on Ternary Optical Computer

Equations (19)

Equations on this page are rendered with MathJax. Learn more.

x = i x i 2 i , x i { 1 ¯ , 0 , 1 } ,
( 4 ) 10 = ( 100 ) 2   or   MSD = ( 1 1 ¯ 00 ) MSD = ( 1 11 ¯ 00 ) MSD ,
( 4 ) 10 = ( 1 ¯ 100 ) MSD = ( 1 ¯ 1100 ) MSD .
1 1 ¯ , 1 ¯ 1 , 0 0.
Step   1 : x i + y i = 2 t i + 1 + w i ,
Step   2 : t i + w i = 2 t i + 1 + w i ,
Step   3 : t i + w i = s i ,
p = a b = i = 0 n 1 p ( i ) = i = 0 n 1 a b i 2 i .
( 14 ) 10 × ( 9 ) 10 = ( 1110 ) MSD × ( 101 1 ¯ ) MSD .
α B = ( α 1 , α 2 , , α N ) ( b 11 b 12 b 1 N b 21 b 22 b 2 N b N 1 b N 2 b N N ) = ( β 1 , β 2 , , β N ) = β ,
β j = i = 0 N α i b i j , j = ( 1 , 2 , , N ) .
E = n 1 log 2 n .
I ( n , N ) = log 2 n + log 2 N .
α = ( α 1 , α 2 ) = ( 3 , 1 ) 10 = ( 11 , 1 1 ¯ ) MSD ,
B = ( b 11 b 12 b 21 b 22 ) = ( 1 2 2 3 ) 10 = ( 1 ¯ 1 10 1 ¯ 0 11 ¯ ) MSD ,
β = α B = ( 11 , 1 1 ¯ ) MSD × ( 1 ¯ 1 10 1 ¯ 0 1 ¯ 1 ¯ ) MSD .
p 1 , 11 = ( 1 ¯ 11 1 ¯ ) MSD = ( 3 ) 10 , p 2 , 21 = ( 00 1 ¯ 0 ) MSD = ( 2 ) 10 , p 1 , 12 = ( 10 1 ¯ 0 ) MSD = ( 6 ) 10 , p 2 , 22 = ( 1 ¯ 11 1 ¯ ) MSD = ( 3 ) 10 .
β 1 = p 1 , 11 + p 2 , 21 , β 2 = p 1 , 12 + p 2 , 22 .
β = α B = ( β 1 , β 2 ) = ( 00 11 ¯ 1 , 01 11 ¯ 1 ) MSD = ( 5 , 3 ) 10 .

Metrics