Abstract

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve huge virtual gate counts that vastly surpass those of currently available VLSIs. By exploiting the large storage capacity of a holographic memory, VLSIs with more than 1 teragate counts will be producible. However, compared with current field programmable gate arrays, conventional ORGAs have one important shortcoming: they cannot be reprogrammed after fabrication. To reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, then reprogrammed outside of the ORGA package using a holographic memory writer. It must then be implemented onto the ORGA package with high precision techniques beyond that which can be provided by manual assembly. Therefore, to improve this shortcoming, this paper proposes what is believed to be the world’s first programmable ORGA architecture with no disassembly. Finally, the availability of this architecture is discussed based on the experimental results.

© 2009 Optical Society of America

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References

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    [CrossRef]
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    [CrossRef]
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    [CrossRef]
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    [CrossRef]
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2008

2007

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Commun. Jpn. 90, 132-139 (2007).

2006

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510-3515(2006).
[CrossRef]

2003

H. Nakano, T. Shindo, T. Kazami, and M. Motomura, “Development of dynamically reconfigurable processor LSI,” NEC Tech. J. 56, 99-102 (2003).

2000

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771 (2000).
[CrossRef]

1999

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).
[CrossRef]

An, X.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” SPIE Critical Review 1999 Euro-American Workshop on Optoelectronic Information Processing (SPIE, 1999), Vol. 74, pp. 265-288.

Ay, S.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” SPIE Critical Review 1999 Euro-American Workshop on Optoelectronic Information Processing (SPIE, 1999), Vol. 74, pp. 265-288.

Barna, S.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771 (2000).
[CrossRef]

Carberry, D.

S. Trimberger, D. Carberry, A. Johnson, and J. Wong, “A time-multiplexed FPGA,” FPGAs for Custom Computing Machines (IEEE, 1997), pp. 22-28.

Dehon, A.

A. Dehon, “Dynamically programmable gate arrays: a step toward increased computational density,” presented at the Fourth Canadian Workshop on Field Programmable Devices, Toronto, Canada, 13-14 May 1996.

Fossum, E.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771 (2000).
[CrossRef]

Hirokari, T.

Johnson, A.

S. Trimberger, D. Carberry, A. Johnson, and J. Wong, “A time-multiplexed FPGA,” FPGAs for Custom Computing Machines (IEEE, 1997), pp. 22-28.

Jones, D.

D. Jones and D. M. Lewis, “A time-multiplexed FPGA architecture for logic emulation,” Custom Integrated Circuits Conference (IEEE, 1995), pp. 495-498.

Kazami, T.

H. Nakano, T. Shindo, T. Kazami, and M. Motomura, “Development of dynamically reconfigurable processor LSI,” NEC Tech. J. 56, 99-102 (2003).

Kobayashi, F.

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Commun. Jpn. 90, 132-139 (2007).

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510-3515(2006).
[CrossRef]

Lewis, D. M.

D. Jones and D. M. Lewis, “A time-multiplexed FPGA architecture for logic emulation,” Custom Integrated Circuits Conference (IEEE, 1995), pp. 495-498.

Liu, W.

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).
[CrossRef]

Miyano, M.

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Commun. Jpn. 90, 132-139 (2007).

Mok, F.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” SPIE Critical Review 1999 Euro-American Workshop on Optoelectronic Information Processing (SPIE, 1999), Vol. 74, pp. 265-288.

Motomura, M.

H. Nakano, T. Shindo, T. Kazami, and M. Motomura, “Development of dynamically reconfigurable processor LSI,” NEC Tech. J. 56, 99-102 (2003).

Mumbru, J.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” SPIE Critical Review 1999 Euro-American Workshop on Optoelectronic Information Processing (SPIE, 1999), Vol. 74, pp. 265-288.

Nakano, H.

H. Nakano, T. Shindo, T. Kazami, and M. Motomura, “Development of dynamically reconfigurable processor LSI,” NEC Tech. J. 56, 99-102 (2003).

Ogiwara, A.

Panotopoulos, G.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” SPIE Critical Review 1999 Euro-American Workshop on Optoelectronic Information Processing (SPIE, 1999), Vol. 74, pp. 265-288.

Psaltis, D.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” SPIE Critical Review 1999 Euro-American Workshop on Optoelectronic Information Processing (SPIE, 1999), Vol. 74, pp. 265-288.

Scalera, S. M.

S. M. Scalera and J. R. Vazquez, in “The design and implementation of a context switching FPGA,” IEEE Symposium on FPGAs for Custom Computing Machines (IEEE, 1998), pp. 78-85.
[CrossRef]

Seto, D.

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array--perfect emulation,” IEEE J. Quantum Electron. 44, 493-500 (2008).
[CrossRef]

Shindo, T.

H. Nakano, T. Shindo, T. Kazami, and M. Motomura, “Development of dynamically reconfigurable processor LSI,” NEC Tech. J. 56, 99-102 (2003).

Trimberger, S.

S. Trimberger, D. Carberry, A. Johnson, and J. Wong, “A time-multiplexed FPGA,” FPGAs for Custom Computing Machines (IEEE, 1997), pp. 22-28.

Vazquez, J. R.

S. M. Scalera and J. R. Vazquez, in “The design and implementation of a context switching FPGA,” IEEE Symposium on FPGAs for Custom Computing Machines (IEEE, 1998), pp. 78-85.
[CrossRef]

Watanabe, M.

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array--perfect emulation,” IEEE J. Quantum Electron. 44, 493-500 (2008).
[CrossRef]

N. Yamaguchi and M. Watanabe, “Liquid crystal holographic configurations for ORGAs,” Appl. Opt. 47, 4692-4700 (2008).
[CrossRef] [PubMed]

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Commun. Jpn. 90, 132-139 (2007).

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510-3515(2006).
[CrossRef]

Wong, J.

S. Trimberger, D. Carberry, A. Johnson, and J. Wong, “A time-multiplexed FPGA,” FPGAs for Custom Computing Machines (IEEE, 1997), pp. 22-28.

Yamaguchi, N.

Zhou, G.

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).
[CrossRef]

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” SPIE Critical Review 1999 Euro-American Workshop on Optoelectronic Information Processing (SPIE, 1999), Vol. 74, pp. 265-288.

Appl. Opt.

Electron. Commun. Jpn.

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Commun. Jpn. 90, 132-139 (2007).

IEEE J. Quantum Electron.

D. Seto and M. Watanabe, “A dynamic optically reconfigurable gate array--perfect emulation,” IEEE J. Quantum Electron. 44, 493-500 (2008).
[CrossRef]

Jpn. J. Appl. Phys.

M. Watanabe and F. Kobayashi, “Dynamic optically reconfigurable gate array,” Jpn. J. Appl. Phys. 45, 3510-3515(2006).
[CrossRef]

NEC Tech. J.

H. Nakano, T. Shindo, T. Kazami, and M. Motomura, “Development of dynamically reconfigurable processor LSI,” NEC Tech. J. 56, 99-102 (2003).

Proc. SPIE

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771 (2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).
[CrossRef]

Other

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” SPIE Critical Review 1999 Euro-American Workshop on Optoelectronic Information Processing (SPIE, 1999), Vol. 74, pp. 265-288.

A. Dehon, “Dynamically programmable gate arrays: a step toward increased computational density,” presented at the Fourth Canadian Workshop on Field Programmable Devices, Toronto, Canada, 13-14 May 1996.

S. M. Scalera and J. R. Vazquez, in “The design and implementation of a context switching FPGA,” IEEE Symposium on FPGAs for Custom Computing Machines (IEEE, 1998), pp. 78-85.
[CrossRef]

S. Trimberger, D. Carberry, A. Johnson, and J. Wong, “A time-multiplexed FPGA,” FPGAs for Custom Computing Machines (IEEE, 1997), pp. 22-28.

D. Jones and D. M. Lewis, “A time-multiplexed FPGA architecture for logic emulation,” Custom Integrated Circuits Conference (IEEE, 1995), pp. 495-498.

Altera Corporation, “Altera Devices,” http://www.altera.com.

Xilinx Inc., “Xilinx Product Data Sheets,” http://www.xilinx.com.

Lattice Semiconductor Corporation, “LatticeECP and EC Family Data Sheet,” http://www.latticesemi.co.jp/products, 2005.

http://www.ipflex.co.jp.

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Figures (12)

Fig. 1
Fig. 1

Overview of a conventional ORGA architecture.

Fig. 2
Fig. 2

Concept of a programmable ORGA architecture and its writer.

Fig. 3
Fig. 3

Experimental system.

Fig. 4
Fig. 4

Photograph of the experimental system. (a) Photograph depicting the writer part and the PORGA part. (b) Magnified image of the PORGA part.

Fig. 5
Fig. 5

Holographic memory patterns displayed on the LC-SLM in a writer.

Fig. 6
Fig. 6

Holographic memory patterns generated by the writer and received on a PAL-SLM in a PORGA. Experimental results were measured by temporarily removing the PAL-SLM and by placing a CCD camera at the same position as the PAL-SLM.

Fig. 7
Fig. 7

CCD-captured images of configuration contexts of the (a) AND circuit, (b) XOR circuit, (c) half-adder circuit, and (d) majority voting circuit, as generated directly from the LC-SLM in a writer. The results show optical configuration contexts in the case of not using a writer. To estimate degraded holographic memory patterns obtained in the case of using a writer, CCD images were captured.

Fig. 8
Fig. 8

CCD-captured images of configuration contexts of the (a) AND circuit, (b) XOR circuit, (c) half-adder circuit, and (d) majority voting circuit, generated from the PAL-SLM.

Fig. 9
Fig. 9

Reconfiguration time ( 37.4 ms ) and execution of an AND circuit.

Fig. 10
Fig. 10

Reconfiguration time ( 37.4 ms ) and execution of an XOR circuit.

Fig. 11
Fig. 11

Reconfiguration time ( 66.5 ms ) and execution of a half-adder circuit.

Fig. 12
Fig. 12

Reconfiguration time ( 37.4 ms ) and execution of a majority voting circuit.

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H ( x 1 , y 1 ) O ( x 2 , y 2 ) sin ( k r ) d x 2 d y 2 , r = Z L 2 + ( x 1 x 2 ) 2 + ( y 1 y 2 ) 2 .
H ( x 1 , y 1 ) = H ( x 1 , y 1 ) H min H max H min .

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