Abstract

An optically reconfigurable gate array (ORGA) system, which consists of an ORGA very large scale integration (VLSI), an easily rewritable liquid crystal holographic memory recording four configuration contexts, and a laser array, is proposed. Circuits on a gate array of the ORGA-VLSI can be programmed rapidly by exploiting large parallel connections between a holographic memory and a gate array VLSI; that programming can be executed even as it is being programmed. Consequently, the gate array can be switched from a certain circuit to another circuit instantaneously. We present a demonstration of the ORGA system and experimental results.

© 2008 Optical Society of America

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  1. Altera Corporation, “Altera Devices,” http://www.altera.com.
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    [CrossRef]
  8. S. Trimberger, D. Carberry, A. Johnson, and J. Wong, “A time-multiplexed FPGA,” in The 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines, 1997. Proceedings (IEEE, 1997), pp. 22-28.
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    [CrossRef] [PubMed]
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    [CrossRef]
  13. J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).
  14. J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” Proc. SPIE CR74, 265-288 (1999).
    [CrossRef]
  15. M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Commun. Jpn. Part II , 90(11), 132-139 (2007).

2007 (1)

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Commun. Jpn. Part II , 90(11), 132-139 (2007).

2003 (1)

H. Nakano, T. Shindo, T. Kazami, and M. Motomura, “Development of dynamically reconfigurable processor LSI,” NEC Tech. J. 56, 99-102 (2003).

1999 (2)

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” Proc. SPIE CR74, 265-288 (1999).
[CrossRef]

1987 (1)

1986 (1)

An, X.

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” Proc. SPIE CR74, 265-288 (1999).
[CrossRef]

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771(2000).
[CrossRef]

Ay, S.

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” Proc. SPIE CR74, 265-288 (1999).
[CrossRef]

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771(2000).
[CrossRef]

Barna, S.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771(2000).
[CrossRef]

Dehon, A.

A. Dehon, “Dynamically programmable gate arrays: a step toward increased computational density,” in Proceedings of the Fourth Canadian Workshop on Field Programmable Devices (University of Toronto, 1996), pp. 47-54.

Fossum, E.

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771(2000).
[CrossRef]

Fukushima, S.

Jones, D.

D. Jones and D. M. Lewis, “A time-multiplexed FPGA architecture for logic emulation,” in Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1995 (IEEE, 1995), pp. 495-498.
[CrossRef] [PubMed]

Kazami, T.

H. Nakano, T. Shindo, T. Kazami, and M. Motomura, “Development of dynamically reconfigurable processor LSI,” NEC Tech. J. 56, 99-102 (2003).

Kobayashi, F.

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Commun. Jpn. Part II , 90(11), 132-139 (2007).

Kurokawa, T.

Lewis, D. M.

D. Jones and D. M. Lewis, “A time-multiplexed FPGA architecture for logic emulation,” in Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1995 (IEEE, 1995), pp. 495-498.
[CrossRef] [PubMed]

Liu, W.

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).

Miyano, M.

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Commun. Jpn. Part II , 90(11), 132-139 (2007).

Mok, F.

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” Proc. SPIE CR74, 265-288 (1999).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771(2000).
[CrossRef]

Motomura, M.

H. Nakano, T. Shindo, T. Kazami, and M. Motomura, “Development of dynamically reconfigurable processor LSI,” NEC Tech. J. 56, 99-102 (2003).

Mumbru, J.

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” Proc. SPIE CR74, 265-288 (1999).
[CrossRef]

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771(2000).
[CrossRef]

Nakano, H.

H. Nakano, T. Shindo, T. Kazami, and M. Motomura, “Development of dynamically reconfigurable processor LSI,” NEC Tech. J. 56, 99-102 (2003).

Panotopoulos, G.

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” Proc. SPIE CR74, 265-288 (1999).
[CrossRef]

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771(2000).
[CrossRef]

Psaltis, D.

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” Proc. SPIE CR74, 265-288 (1999).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771(2000).
[CrossRef]

Scalera, S. M.

S. M. Scalera and J. R. Vazquez, “The design and implementation of a context switching FPGA,” in IEEE Symposium on FPGAs for Custom Computing Machines, 1998. Proceedings (IEEE, 1998), pp. 78-85.
[CrossRef]

Shindo, T.

H. Nakano, T. Shindo, T. Kazami, and M. Motomura, “Development of dynamically reconfigurable processor LSI,” NEC Tech. J. 56, 99-102 (2003).

Trimberger, S.

S. Trimberger, D. Carberry, A. Johnson, and J. Wong, “A time-multiplexed FPGA,” in The 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines, 1997. Proceedings (IEEE, 1997), pp. 22-28.

Vazquez, J. R.

S. M. Scalera and J. R. Vazquez, “The design and implementation of a context switching FPGA,” in IEEE Symposium on FPGAs for Custom Computing Machines, 1998. Proceedings (IEEE, 1998), pp. 78-85.
[CrossRef]

Watanabe, M.

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Commun. Jpn. Part II , 90(11), 132-139 (2007).

Yatagai, T.

Zhou, G.

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” Proc. SPIE CR74, 265-288 (1999).
[CrossRef]

Electron. Commun. Jpn. Part II (1)

M. Miyano, M. Watanabe, and F. Kobayashi, “Optically differential reconfigurable gate array,” Electron. Commun. Jpn. Part II , 90(11), 132-139 (2007).

NEC Tech. J. (1)

H. Nakano, T. Shindo, T. Kazami, and M. Motomura, “Development of dynamically reconfigurable processor LSI,” NEC Tech. J. 56, 99-102 (2003).

Opt. Lett. (2)

Proc. SPIE (3)

J. Mumbru, G. Panotopoulos, D. Psaltis, X. An, F. Mok, S. Ay, S. Barna, and E. Fossum, “Optically programmable gate array,” Proc. SPIE 4089, 763-771(2000).
[CrossRef]

J. Mumbru, G. Zhou, X. An, W. Liu, G. Panotopoulos, F. Mok, and D. Psaltis, “Optical memory for computing and information processing,” Proc. SPIE 3804, 14-24 (1999).

J. Mumbru, G. Zhou, S. Ay, X. An, G. Panotopoulos, F. Mok, and D. Psaltis, “Optically reconfigurable processors,” Proc. SPIE CR74, 265-288 (1999).
[CrossRef]

Other (8)

A. Dehon, “Dynamically programmable gate arrays: a step toward increased computational density,” in Proceedings of the Fourth Canadian Workshop on Field Programmable Devices (University of Toronto, 1996), pp. 47-54.

S. M. Scalera and J. R. Vazquez, “The design and implementation of a context switching FPGA,” in IEEE Symposium on FPGAs for Custom Computing Machines, 1998. Proceedings (IEEE, 1998), pp. 78-85.
[CrossRef]

S. Trimberger, D. Carberry, A. Johnson, and J. Wong, “A time-multiplexed FPGA,” in The 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines, 1997. Proceedings (IEEE, 1997), pp. 22-28.

D. Jones and D. M. Lewis, “A time-multiplexed FPGA architecture for logic emulation,” in Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1995 (IEEE, 1995), pp. 495-498.
[CrossRef] [PubMed]

Altera Corporation, “Altera Devices,” http://www.altera.com.

Xilinx Inc., “Xilinx Product Data Sheets,” http://www.xilinx.com.

Lattice Semiconductor Corporation, “LatticeECP and EC Family Data Sheet,” http://www.latticesemi.co.jp/products, 2005.

http://www.ipflex.co.jp.

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Figures (10)

Fig. 1
Fig. 1

Overview of an ORGA.

Fig. 2
Fig. 2

Gate-array structure of a fabricated ODRGA. Block diagrams of (a) a gate array, (b) an optically reconfigurable logic block, (c) an optically reconfigurable switching matrix, and (d) an optically reconfigurable I/O bit.

Fig. 3
Fig. 3

Schematic diagram of an array of optically differential reconfiguration circuits.

Fig. 4
Fig. 4

Photograph of an ODRGA-VLSI board with a fabricated ORGA-VLSI chip and a CAD layout of the ODRGA-VLSI. The ODRGA-VLSI was fabricated by using a 0.35 μm three-metal 4.9 mm × 4.9 mm CMOS process chip. The gate count of a gate array on the chip is 68. In all, 340 photodiodes are used for optical configurations.

Fig. 5
Fig. 5

Experimental system setup of an ODRGA architecture.

Fig. 6
Fig. 6

Experimental system.

Fig. 7
Fig. 7

Sample configuration contexts of an OR circuit, an AND circuit, a NAND circuit, and a NOR circuit.

Fig. 8
Fig. 8

Holographic memory pattern that is used for generating four configuration context patterns for an ORGA-VLSI and is displayed on an LC-SLM. The holographic information of an OR circuit, an AND circuit, a NAND circuit, and a NOR circuit are stored, respectively, on the upper left region, the upper right region, the lower left region, and the lower right region. Each holographic area consist of 300 × 300 pixels, the size of which is 14 μm × 14 μm . The x- and y-direction distances between holographic regions were designed as 140 μm .

Fig. 9
Fig. 9

Experimental results of configuration context patterns of an OR circuit, an AND circuit, a NAND circuit, and a NOR circuit: CCD-received results at the ORGA-VLSI position, as reconstructed from the holographic memories of Fig. 8. Each bright pixel represents a binary value ‘1’; each black pixel represents a binary value ‘0.’

Fig. 10
Fig. 10

Implementation results of an OR circuit, an AND circuit, a NAND circuit, and a NOR circuit. It was confirmed that, after raising the configuration clock signal, each circuit is configured correctly on a gate array of ORGA-VLSIs and can be executed correctly. The reconfiguration times of the OR circuit, the AND circuit, the NAND circuit, and the NOR circuit were measured as 1.397, 2.396, 2.196, and 2.196 ms , respectively.

Tables (1)

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Table 1 ODRGA-VLSI Specifications

Equations (4)

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H ( x 1 , y 1 ) O ( x 2 , y 2 ) sin ( k r ) d x 2 d y 2 , r = Z L 2 + ( x 1 x 2 ) 2 + ( y 1 y 2 ) 2 .
H ( x 1 , y 1 ) = H ( x 1 , y 1 ) H min H max H min .
Δ T opt = h ν η e P PD ( C J + C L ) ( V DD V th ) ,
Δ T reconf = Δ T opt + Δ T RPW ,

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