Abstract

We examine the benefits of electrical isolation in intrachip optical signaling. We calculate the delay and energy metrics of an optical interconnect with fanout driving an electrical load. By examining fanout and including load drivers into delay equations, we make a shift from the general trend of looking at optical interconnects as a replacement for long parasitic wires. Our calculations show that optical fanout provides a large improvement in an Eτ2 (energy delay squared) metric and improves performance even at very short intrachip distances. The break-even length corresponds to the wiring length of 250 minimum-size inverters that are compactly laid out. These results provide a compelling reason to further examine the implementation of optical interconnects.

© 2005 Optical Society of America

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References

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2004 (1)

2003 (7)

A. Naeemi, A. V. Mule, J. D. Meindl, “Partition length between board-level electrical and optical interconnects,” Proc. IEEE Interconnect Technol. Conf.230–232 (2003).
[CrossRef]

M. B. Venditti, E. Laprise, J. Faucher, P.-O. Laprise, J. E. A. Lugo, D. V. Plant, “Design and test of an optoelectronic-VLSI chip with 540-element receiver–transmitter arrays using differential optical signaling,” IEEE J. Sel. Top. Quantum Electron. 9, 361–379 (2003).
[CrossRef]

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

J. H. Collet, F. Caignet, F. Sellaye, D. Litaize, “Performance constraints for on-chip optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 425–432 (2003).
[CrossRef]

C. Debaes, A. Bhatnagar, D. Agarwal, R. Chen, G. A. Keeler, N. C. Helman, H. Thienpont, D. A. Miller, “Receiverless optical clock injection for clock distribution networks,” IEEE J. Sel. Top. Quantum Electron. 9, 400–409 (2003).
[CrossRef]

D. Huang, T. Sze, A. Landin, R. Lytel, H. L. Davidson, “Optical interconnects: out of the box forever?” IEEE J. Sel. Top. Quantum Electron. 9, 614–623 (2003).
[CrossRef]

M. W. Haney, H. Thienpont, T. Yoshimura, “Introduction to the issue on optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 347–349 (2003).
[CrossRef]

2002 (1)

A. V. Mule, E. N. Glytsis, T. K. Gaylord, J. D. Meindl, “Electrical and optical clock distribution networks for gigascale microprocessors,” IEEE Trans. VLSI Syst. 10, 582–594 (2002).
[CrossRef]

2001 (2)

J. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. Souri, K. Banerjee, K. Saraswat, A. Rahman, R. Reif, J. Meindl, “Interconnect limits on gigascale integration in the 21st century,” Proc. IEEE 89, 305–324 (2001).
[CrossRef]

R. Ho, K. W. Mai, M. A. Horowitz, “The future of wires,” Proc. IEEE 89, 490–504 (2001).
[CrossRef]

2000 (1)

A. Levi, “Optical interconnects in systems,” Proc. IEEE 88, 750–757 (2000).
[CrossRef]

1999 (2)

F. E. Kiamilev, A. V. Krishnamoorthy, “A high-speed 32-channel CMOS VCSEL driver with built-in self-test and clock generation circuitry,” IEEE J. Sel. Top. Quantum Electron. 5, 287–295 (1999).
[CrossRef]

M. Ingels, M. Steyaert, “A 1-gbit/s, 0.7-μm CMOS optical receiver with full rail-to-rail output swing,” IEEE J. Solid-State Circuits 34, 971–977 (1999).
[CrossRef]

1998 (1)

1997 (1)

A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, T. K. Lee, “The design of an asynchronous MIPS R3000 microprocessor,” Proc. Adv. Res. VLSI164–181 (1997).
[CrossRef]

1996 (1)

A. V. Krishnamoorthy, D. A. B. Miller, “Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Sel. Top. Quantum Electron. 2, 55–76 (1996).
[CrossRef]

Agarwal, D.

C. Debaes, A. Bhatnagar, D. Agarwal, R. Chen, G. A. Keeler, N. C. Helman, H. Thienpont, D. A. Miller, “Receiverless optical clock injection for clock distribution networks,” IEEE J. Sel. Top. Quantum Electron. 9, 400–409 (2003).
[CrossRef]

Apsel, A.

T. Yin, A. Apsel, A. M. Pappu, C. Reungsinpinya, A. Khimani, “Optical interconnects in commercial BiCMOS,” in Optoelectronic Integration in Silicon, D. J. Robbins, G. E. Jabbour, eds., Proc. SPIE5357, 1–10 (2004).
[CrossRef]

Araki, H.

S. Wakayama, K. Gotoh, M. Saito, H. Araki, T. Shing Cheung, J. Ogawa, H. Tamura, “10-ns row cycle DRAM using temporal data storage buffer architecture,” in Digest of Technical Papers, Symposium on VLSI Circuits (IEEE, 1998), pp. 12–15.

Armendariz, M. G.

V. M. Hietala, K. L. Lear, M. G. Armendariz, C. P. Tigges, H. Q. Hou, J. C. Zolper, “Electrical characterization and application of very high speed vertical cavity surface emitting lasers,” in IEEE MTT-S International Microwave Symposium Digest, Vol. 1 (Institute of Electrical and Electronics Engineers, 1997), pp. 355–358.

Banerjee, K.

J. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. Souri, K. Banerjee, K. Saraswat, A. Rahman, R. Reif, J. Meindl, “Interconnect limits on gigascale integration in the 21st century,” Proc. IEEE 89, 305–324 (2001).
[CrossRef]

Beylansky, M.

J. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. Souri, K. Banerjee, K. Saraswat, A. Rahman, R. Reif, J. Meindl, “Interconnect limits on gigascale integration in the 21st century,” Proc. IEEE 89, 305–324 (2001).
[CrossRef]

Bhatnagar, A.

C. Debaes, A. Bhatnagar, D. Agarwal, R. Chen, G. A. Keeler, N. C. Helman, H. Thienpont, D. A. Miller, “Receiverless optical clock injection for clock distribution networks,” IEEE J. Sel. Top. Quantum Electron. 9, 400–409 (2003).
[CrossRef]

Caignet, F.

J. H. Collet, F. Caignet, F. Sellaye, D. Litaize, “Performance constraints for on-chip optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 425–432 (2003).
[CrossRef]

Chen, R.

C. Debaes, A. Bhatnagar, D. Agarwal, R. Chen, G. A. Keeler, N. C. Helman, H. Thienpont, D. A. Miller, “Receiverless optical clock injection for clock distribution networks,” IEEE J. Sel. Top. Quantum Electron. 9, 400–409 (2003).
[CrossRef]

Collet, J. H.

J. H. Collet, F. Caignet, F. Sellaye, D. Litaize, “Performance constraints for on-chip optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 425–432 (2003).
[CrossRef]

Cook, C.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Cummings, U.

A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, T. K. Lee, “The design of an asynchronous MIPS R3000 microprocessor,” Proc. Adv. Res. VLSI164–181 (1997).
[CrossRef]

Cunningham, J. E.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Dally, W. J.

W. J. Dally, J. W. Poulton, Digital Systems Engineering (Cambridge University, 1998).
[CrossRef]

Davidson, H. L.

D. Huang, T. Sze, A. Landin, R. Lytel, H. L. Davidson, “Optical interconnects: out of the box forever?” IEEE J. Sel. Top. Quantum Electron. 9, 614–623 (2003).
[CrossRef]

Davis, J.

J. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. Souri, K. Banerjee, K. Saraswat, A. Rahman, R. Reif, J. Meindl, “Interconnect limits on gigascale integration in the 21st century,” Proc. IEEE 89, 305–324 (2001).
[CrossRef]

Debaes, C.

C. Debaes, A. Bhatnagar, D. Agarwal, R. Chen, G. A. Keeler, N. C. Helman, H. Thienpont, D. A. Miller, “Receiverless optical clock injection for clock distribution networks,” IEEE J. Sel. Top. Quantum Electron. 9, 400–409 (2003).
[CrossRef]

Dolfi, D. W.

Esener, S. C.

Eshraghian, K.

N. H. E. Weste, K. Eshraghian, Principles of CMOS VLSI Design (Addison-Wesley, 1994).

Faucher, J.

M. B. Venditti, E. Laprise, J. Faucher, P.-O. Laprise, J. E. A. Lugo, D. V. Plant, “Design and test of an optoelectronic-VLSI chip with 540-element receiver–transmitter arrays using differential optical signaling,” IEEE J. Sel. Top. Quantum Electron. 9, 361–379 (2003).
[CrossRef]

Flower, G. M.

Gaylord, T. K.

A. V. Mule, E. N. Glytsis, T. K. Gaylord, J. D. Meindl, “Electrical and optical clock distribution networks for gigascale microprocessors,” IEEE Trans. VLSI Syst. 10, 582–594 (2002).
[CrossRef]

Ger, G.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Giboney, K. S.

Glytsis, E. N.

A. V. Mule, E. N. Glytsis, T. K. Gaylord, J. D. Meindl, “Electrical and optical clock distribution networks for gigascale microprocessors,” IEEE Trans. VLSI Syst. 10, 582–594 (2002).
[CrossRef]

Goossen, K. W.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Gotoh, K.

S. Wakayama, K. Gotoh, M. Saito, H. Araki, T. Shing Cheung, J. Ogawa, H. Tamura, “10-ns row cycle DRAM using temporal data storage buffer architecture,” in Digest of Technical Papers, Symposium on VLSI Circuits (IEEE, 1998), pp. 12–15.

Grot, A.

Gruhlke, R. W.

Haney, M. W.

M. W. Haney, H. Thienpont, T. Yoshimura, “Introduction to the issue on optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 347–349 (2003).
[CrossRef]

Hargrove, A.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Harris, D.

I. Sutherland, B. Sproull, D. Harris, Logical Effort: Designing Fast CMOS Circuits (Morgan Kauffman, 1999).

Heatley, D. J.

D. J. Heatley, “Optical receivers,” in Design of Analog–Digital VLSI Circuits for Telecommunications and Signal Processing, Y. T. Jose E. Franca, ed. (Prentice-Hall, 1994), Chap. 5.

Helman, N. C.

C. Debaes, A. Bhatnagar, D. Agarwal, R. Chen, G. A. Keeler, N. C. Helman, H. Thienpont, D. A. Miller, “Receiverless optical clock injection for clock distribution networks,” IEEE J. Sel. Top. Quantum Electron. 9, 400–409 (2003).
[CrossRef]

Hietala, V. M.

V. M. Hietala, K. L. Lear, M. G. Armendariz, C. P. Tigges, H. Q. Hou, J. C. Zolper, “Electrical characterization and application of very high speed vertical cavity surface emitting lasers,” in IEEE MTT-S International Microwave Symposium Digest, Vol. 1 (Institute of Electrical and Electronics Engineers, 1997), pp. 355–358.

Ho, R.

R. Ho, K. W. Mai, M. A. Horowitz, “The future of wires,” Proc. IEEE 89, 490–504 (2001).
[CrossRef]

Horowitz, M. A.

R. Ho, K. W. Mai, M. A. Horowitz, “The future of wires,” Proc. IEEE 89, 490–504 (2001).
[CrossRef]

Hou, H. Q.

V. M. Hietala, K. L. Lear, M. G. Armendariz, C. P. Tigges, H. Q. Hou, J. C. Zolper, “Electrical characterization and application of very high speed vertical cavity surface emitting lasers,” in IEEE MTT-S International Microwave Symposium Digest, Vol. 1 (Institute of Electrical and Electronics Engineers, 1997), pp. 355–358.

Huang, D.

D. Huang, T. Sze, A. Landin, R. Lytel, H. L. Davidson, “Optical interconnects: out of the box forever?” IEEE J. Sel. Top. Quantum Electron. 9, 614–623 (2003).
[CrossRef]

Ingels, M.

M. Ingels, M. Steyaert, “A 1-gbit/s, 0.7-μm CMOS optical receiver with full rail-to-rail output swing,” IEEE J. Solid-State Circuits 34, 971–977 (1999).
[CrossRef]

Jan, W. Y.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Kaloyeros, A.

J. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. Souri, K. Banerjee, K. Saraswat, A. Rahman, R. Reif, J. Meindl, “Interconnect limits on gigascale integration in the 21st century,” Proc. IEEE 89, 305–324 (2001).
[CrossRef]

Keeler, G. A.

C. Debaes, A. Bhatnagar, D. Agarwal, R. Chen, G. A. Keeler, N. C. Helman, H. Thienpont, D. A. Miller, “Receiverless optical clock injection for clock distribution networks,” IEEE J. Sel. Top. Quantum Electron. 9, 400–409 (2003).
[CrossRef]

Khimani, A.

T. Yin, A. Apsel, A. M. Pappu, C. Reungsinpinya, A. Khimani, “Optical interconnects in commercial BiCMOS,” in Optoelectronic Integration in Silicon, D. J. Robbins, G. E. Jabbour, eds., Proc. SPIE5357, 1–10 (2004).
[CrossRef]

Kiamilev, F. E.

F. E. Kiamilev, A. V. Krishnamoorthy, “A high-speed 32-channel CMOS VCSEL driver with built-in self-test and clock generation circuitry,” IEEE J. Sel. Top. Quantum Electron. 5, 287–295 (1999).
[CrossRef]

Kim, H. H.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Krause, R.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Krishnamoorthy, A. V.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

F. E. Kiamilev, A. V. Krishnamoorthy, “A high-speed 32-channel CMOS VCSEL driver with built-in self-test and clock generation circuitry,” IEEE J. Sel. Top. Quantum Electron. 5, 287–295 (1999).
[CrossRef]

A. V. Krishnamoorthy, D. A. B. Miller, “Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Sel. Top. Quantum Electron. 2, 55–76 (1996).
[CrossRef]

Landin, A.

D. Huang, T. Sze, A. Landin, R. Lytel, H. L. Davidson, “Optical interconnects: out of the box forever?” IEEE J. Sel. Top. Quantum Electron. 9, 614–623 (2003).
[CrossRef]

Laprise, E.

M. B. Venditti, E. Laprise, J. Faucher, P.-O. Laprise, J. E. A. Lugo, D. V. Plant, “Design and test of an optoelectronic-VLSI chip with 540-element receiver–transmitter arrays using differential optical signaling,” IEEE J. Sel. Top. Quantum Electron. 9, 361–379 (2003).
[CrossRef]

Laprise, P.-O.

M. B. Venditti, E. Laprise, J. Faucher, P.-O. Laprise, J. E. A. Lugo, D. V. Plant, “Design and test of an optoelectronic-VLSI chip with 540-element receiver–transmitter arrays using differential optical signaling,” IEEE J. Sel. Top. Quantum Electron. 9, 361–379 (2003).
[CrossRef]

Law, B.

Lear, K. L.

V. M. Hietala, K. L. Lear, M. G. Armendariz, C. P. Tigges, H. Q. Hou, J. C. Zolper, “Electrical characterization and application of very high speed vertical cavity surface emitting lasers,” in IEEE MTT-S International Microwave Symposium Digest, Vol. 1 (Institute of Electrical and Electronics Engineers, 1997), pp. 355–358.

Lee, T. K.

A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, T. K. Lee, “The design of an asynchronous MIPS R3000 microprocessor,” Proc. Adv. Res. VLSI164–181 (1997).
[CrossRef]

Levi, A.

A. Levi, “Optical interconnects in systems,” Proc. IEEE 88, 750–757 (2000).
[CrossRef]

Lines, A.

A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, T. K. Lee, “The design of an asynchronous MIPS R3000 microprocessor,” Proc. Adv. Res. VLSI164–181 (1997).
[CrossRef]

Link, C.-K.

Litaize, D.

J. H. Collet, F. Caignet, F. Sellaye, D. Litaize, “Performance constraints for on-chip optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 425–432 (2003).
[CrossRef]

Lugo, J. E. A.

M. B. Venditti, E. Laprise, J. Faucher, P.-O. Laprise, J. E. A. Lugo, D. V. Plant, “Design and test of an optoelectronic-VLSI chip with 540-element receiver–transmitter arrays using differential optical signaling,” IEEE J. Sel. Top. Quantum Electron. 9, 361–379 (2003).
[CrossRef]

Lytel, R.

D. Huang, T. Sze, A. Landin, R. Lytel, H. L. Davidson, “Optical interconnects: out of the box forever?” IEEE J. Sel. Top. Quantum Electron. 9, 614–623 (2003).
[CrossRef]

Mai, K. W.

R. Ho, K. W. Mai, M. A. Horowitz, “The future of wires,” Proc. IEEE 89, 490–504 (2001).
[CrossRef]

Manges, M.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Manohar, R.

A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, T. K. Lee, “The design of an asynchronous MIPS R3000 microprocessor,” Proc. Adv. Res. VLSI164–181 (1997).
[CrossRef]

Marchand, P. J.

Martin, A. J.

A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, T. K. Lee, “The design of an asynchronous MIPS R3000 microprocessor,” Proc. Adv. Res. VLSI164–181 (1997).
[CrossRef]

Meindl, J.

J. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. Souri, K. Banerjee, K. Saraswat, A. Rahman, R. Reif, J. Meindl, “Interconnect limits on gigascale integration in the 21st century,” Proc. IEEE 89, 305–324 (2001).
[CrossRef]

Meindl, J. D.

A. Naeemi, A. V. Mule, J. D. Meindl, “Partition length between board-level electrical and optical interconnects,” Proc. IEEE Interconnect Technol. Conf.230–232 (2003).
[CrossRef]

A. V. Mule, E. N. Glytsis, T. K. Gaylord, J. D. Meindl, “Electrical and optical clock distribution networks for gigascale microprocessors,” IEEE Trans. VLSI Syst. 10, 582–594 (2002).
[CrossRef]

Miller, D. A.

C. Debaes, A. Bhatnagar, D. Agarwal, R. Chen, G. A. Keeler, N. C. Helman, H. Thienpont, D. A. Miller, “Receiverless optical clock injection for clock distribution networks,” IEEE J. Sel. Top. Quantum Electron. 9, 400–409 (2003).
[CrossRef]

Miller, D. A. B.

A. V. Krishnamoorthy, D. A. B. Miller, “Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Sel. Top. Quantum Electron. 2, 55–76 (1996).
[CrossRef]

Mirkarimi, L. W.

Morrissey, M.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Mule, A. V.

A. Naeemi, A. V. Mule, J. D. Meindl, “Partition length between board-level electrical and optical interconnects,” Proc. IEEE Interconnect Technol. Conf.230–232 (2003).
[CrossRef]

A. V. Mule, E. N. Glytsis, T. K. Gaylord, J. D. Meindl, “Electrical and optical clock distribution networks for gigascale microprocessors,” IEEE Trans. VLSI Syst. 10, 582–594 (2002).
[CrossRef]

Naeemi, A.

A. Naeemi, A. V. Mule, J. D. Meindl, “Partition length between board-level electrical and optical interconnects,” Proc. IEEE Interconnect Technol. Conf.230–232 (2003).
[CrossRef]

Nystrom, M.

A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, T. K. Lee, “The design of an asynchronous MIPS R3000 microprocessor,” Proc. Adv. Res. VLSI164–181 (1997).
[CrossRef]

Ogata, K.

K. Ogata, Modern Control Engineering (Prentice-Hall, 1970).

Ogawa, J.

S. Wakayama, K. Gotoh, M. Saito, H. Araki, T. Shing Cheung, J. Ogawa, H. Tamura, “10-ns row cycle DRAM using temporal data storage buffer architecture,” in Digest of Technical Papers, Symposium on VLSI Circuits (IEEE, 1998), pp. 12–15.

Pappu, A. M.

T. Yin, A. Apsel, A. M. Pappu, C. Reungsinpinya, A. Khimani, “Optical interconnects in commercial BiCMOS,” in Optoelectronic Integration in Silicon, D. J. Robbins, G. E. Jabbour, eds., Proc. SPIE5357, 1–10 (2004).
[CrossRef]

Penzes, P.

A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, T. K. Lee, “The design of an asynchronous MIPS R3000 microprocessor,” Proc. Adv. Res. VLSI164–181 (1997).
[CrossRef]

Perinpanayagam, M.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Persaud, A.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Plant, D. V.

M. B. Venditti, E. Laprise, J. Faucher, P.-O. Laprise, J. E. A. Lugo, D. V. Plant, “Design and test of an optoelectronic-VLSI chip with 540-element receiver–transmitter arrays using differential optical signaling,” IEEE J. Sel. Top. Quantum Electron. 9, 361–379 (2003).
[CrossRef]

Poulton, J. W.

W. J. Dally, J. W. Poulton, Digital Systems Engineering (Cambridge University, 1998).
[CrossRef]

Rahman, A.

J. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. Souri, K. Banerjee, K. Saraswat, A. Rahman, R. Reif, J. Meindl, “Interconnect limits on gigascale integration in the 21st century,” Proc. IEEE 89, 305–324 (2001).
[CrossRef]

Rankin, G.

Reif, R.

J. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. Souri, K. Banerjee, K. Saraswat, A. Rahman, R. Reif, J. Meindl, “Interconnect limits on gigascale integration in the 21st century,” Proc. IEEE 89, 305–324 (2001).
[CrossRef]

Reungsinpinya, C.

T. Yin, A. Apsel, A. M. Pappu, C. Reungsinpinya, A. Khimani, “Optical interconnects in commercial BiCMOS,” in Optoelectronic Integration in Silicon, D. J. Robbins, G. E. Jabbour, eds., Proc. SPIE5357, 1–10 (2004).
[CrossRef]

Rosenau, S. A.

Saito, M.

S. Wakayama, K. Gotoh, M. Saito, H. Araki, T. Shing Cheung, J. Ogawa, H. Tamura, “10-ns row cycle DRAM using temporal data storage buffer architecture,” in Digest of Technical Papers, Symposium on VLSI Circuits (IEEE, 1998), pp. 12–15.

Saraswat, K.

J. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. Souri, K. Banerjee, K. Saraswat, A. Rahman, R. Reif, J. Meindl, “Interconnect limits on gigascale integration in the 21st century,” Proc. IEEE 89, 305–324 (2001).
[CrossRef]

Sellaye, F.

J. H. Collet, F. Caignet, F. Sellaye, D. Litaize, “Performance constraints for on-chip optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 425–432 (2003).
[CrossRef]

Shevchuk, G. J.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Shing Cheung, T.

S. Wakayama, K. Gotoh, M. Saito, H. Araki, T. Shing Cheung, J. Ogawa, H. Tamura, “10-ns row cycle DRAM using temporal data storage buffer architecture,” in Digest of Technical Papers, Symposium on VLSI Circuits (IEEE, 1998), pp. 12–15.

Simon, J. N.

Sinyansky, V.

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

Souri, S.

J. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. Souri, K. Banerjee, K. Saraswat, A. Rahman, R. Reif, J. Meindl, “Interconnect limits on gigascale integration in the 21st century,” Proc. IEEE 89, 305–324 (2001).
[CrossRef]

Southworth, R.

A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, T. K. Lee, “The design of an asynchronous MIPS R3000 microprocessor,” Proc. Adv. Res. VLSI164–181 (1997).
[CrossRef]

Sproull, B.

I. Sutherland, B. Sproull, D. Harris, Logical Effort: Designing Fast CMOS Circuits (Morgan Kauffman, 1999).

Steyaert, M.

M. Ingels, M. Steyaert, “A 1-gbit/s, 0.7-μm CMOS optical receiver with full rail-to-rail output swing,” IEEE J. Solid-State Circuits 34, 971–977 (1999).
[CrossRef]

Sutherland, I.

I. Sutherland, B. Sproull, D. Harris, Logical Effort: Designing Fast CMOS Circuits (Morgan Kauffman, 1999).

Sze, T.

D. Huang, T. Sze, A. Landin, R. Lytel, H. L. Davidson, “Optical interconnects: out of the box forever?” IEEE J. Sel. Top. Quantum Electron. 9, 614–623 (2003).
[CrossRef]

Tamura, H.

S. Wakayama, K. Gotoh, M. Saito, H. Araki, T. Shing Cheung, J. Ogawa, H. Tamura, “10-ns row cycle DRAM using temporal data storage buffer architecture,” in Digest of Technical Papers, Symposium on VLSI Circuits (IEEE, 1998), pp. 12–15.

Tan, M. R. T.

Tandon, A.

Thienpont, H.

M. W. Haney, H. Thienpont, T. Yoshimura, “Introduction to the issue on optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 347–349 (2003).
[CrossRef]

C. Debaes, A. Bhatnagar, D. Agarwal, R. Chen, G. A. Keeler, N. C. Helman, H. Thienpont, D. A. Miller, “Receiverless optical clock injection for clock distribution networks,” IEEE J. Sel. Top. Quantum Electron. 9, 400–409 (2003).
[CrossRef]

Tigges, C. P.

V. M. Hietala, K. L. Lear, M. G. Armendariz, C. P. Tigges, H. Q. Hou, J. C. Zolper, “Electrical characterization and application of very high speed vertical cavity surface emitting lasers,” in IEEE MTT-S International Microwave Symposium Digest, Vol. 1 (Institute of Electrical and Electronics Engineers, 1997), pp. 355–358.

Venditti, M. B.

M. B. Venditti, E. Laprise, J. Faucher, P.-O. Laprise, J. E. A. Lugo, D. V. Plant, “Design and test of an optoelectronic-VLSI chip with 540-element receiver–transmitter arrays using differential optical signaling,” IEEE J. Sel. Top. Quantum Electron. 9, 361–379 (2003).
[CrossRef]

Venkatesan, R.

J. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. Souri, K. Banerjee, K. Saraswat, A. Rahman, R. Reif, J. Meindl, “Interconnect limits on gigascale integration in the 21st century,” Proc. IEEE 89, 305–324 (2001).
[CrossRef]

Wakayama, S.

S. Wakayama, K. Gotoh, M. Saito, H. Araki, T. Shing Cheung, J. Ogawa, H. Tamura, “10-ns row cycle DRAM using temporal data storage buffer architecture,” in Digest of Technical Papers, Symposium on VLSI Circuits (IEEE, 1998), pp. 12–15.

Weste, N. H. E.

N. H. E. Weste, K. Eshraghian, Principles of CMOS VLSI Design (Addison-Wesley, 1994).

Windover, L. A. B.

Xia, H.

Yayla, G. I.

Yin, T.

T. Yin, A. Apsel, A. M. Pappu, C. Reungsinpinya, A. Khimani, “Optical interconnects in commercial BiCMOS,” in Optoelectronic Integration in Silicon, D. J. Robbins, G. E. Jabbour, eds., Proc. SPIE5357, 1–10 (2004).
[CrossRef]

Yoshimura, T.

M. W. Haney, H. Thienpont, T. Yoshimura, “Introduction to the issue on optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 347–349 (2003).
[CrossRef]

Zolper, J. C.

V. M. Hietala, K. L. Lear, M. G. Armendariz, C. P. Tigges, H. Q. Hou, J. C. Zolper, “Electrical characterization and application of very high speed vertical cavity surface emitting lasers,” in IEEE MTT-S International Microwave Symposium Digest, Vol. 1 (Institute of Electrical and Electronics Engineers, 1997), pp. 355–358.

Appl. Opt. (1)

IEEE J. Sel. Top. Quantum Electron. (8)

A. V. Krishnamoorthy, D. A. B. Miller, “Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Sel. Top. Quantum Electron. 2, 55–76 (1996).
[CrossRef]

M. B. Venditti, E. Laprise, J. Faucher, P.-O. Laprise, J. E. A. Lugo, D. V. Plant, “Design and test of an optoelectronic-VLSI chip with 540-element receiver–transmitter arrays using differential optical signaling,” IEEE J. Sel. Top. Quantum Electron. 9, 361–379 (2003).
[CrossRef]

C. Cook, J. E. Cunningham, A. Hargrove, G. Ger, K. W. Goossen, W. Y. Jan, H. H. Kim, R. Krause, M. Manges, M. Morrissey, M. Perinpanayagam, A. Persaud, G. J. Shevchuk, V. Sinyansky, A. V. Krishnamoorthy, “A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology,” IEEE J. Sel. Top. Quantum Electron. 9, 387–399 (2003).
[CrossRef]

J. H. Collet, F. Caignet, F. Sellaye, D. Litaize, “Performance constraints for on-chip optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 425–432 (2003).
[CrossRef]

D. Huang, T. Sze, A. Landin, R. Lytel, H. L. Davidson, “Optical interconnects: out of the box forever?” IEEE J. Sel. Top. Quantum Electron. 9, 614–623 (2003).
[CrossRef]

C. Debaes, A. Bhatnagar, D. Agarwal, R. Chen, G. A. Keeler, N. C. Helman, H. Thienpont, D. A. Miller, “Receiverless optical clock injection for clock distribution networks,” IEEE J. Sel. Top. Quantum Electron. 9, 400–409 (2003).
[CrossRef]

F. E. Kiamilev, A. V. Krishnamoorthy, “A high-speed 32-channel CMOS VCSEL driver with built-in self-test and clock generation circuitry,” IEEE J. Sel. Top. Quantum Electron. 5, 287–295 (1999).
[CrossRef]

M. W. Haney, H. Thienpont, T. Yoshimura, “Introduction to the issue on optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 347–349 (2003).
[CrossRef]

IEEE J. Solid-State Circuits (1)

M. Ingels, M. Steyaert, “A 1-gbit/s, 0.7-μm CMOS optical receiver with full rail-to-rail output swing,” IEEE J. Solid-State Circuits 34, 971–977 (1999).
[CrossRef]

IEEE Trans. VLSI Syst. (1)

A. V. Mule, E. N. Glytsis, T. K. Gaylord, J. D. Meindl, “Electrical and optical clock distribution networks for gigascale microprocessors,” IEEE Trans. VLSI Syst. 10, 582–594 (2002).
[CrossRef]

J. Lightwave Technol. (1)

Proc. Adv. Res. VLSI (1)

A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, T. K. Lee, “The design of an asynchronous MIPS R3000 microprocessor,” Proc. Adv. Res. VLSI164–181 (1997).
[CrossRef]

Proc. IEEE (3)

A. Levi, “Optical interconnects in systems,” Proc. IEEE 88, 750–757 (2000).
[CrossRef]

R. Ho, K. W. Mai, M. A. Horowitz, “The future of wires,” Proc. IEEE 89, 490–504 (2001).
[CrossRef]

J. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. Souri, K. Banerjee, K. Saraswat, A. Rahman, R. Reif, J. Meindl, “Interconnect limits on gigascale integration in the 21st century,” Proc. IEEE 89, 305–324 (2001).
[CrossRef]

Proc. IEEE Interconnect Technol. Conf. (1)

A. Naeemi, A. V. Mule, J. D. Meindl, “Partition length between board-level electrical and optical interconnects,” Proc. IEEE Interconnect Technol. Conf.230–232 (2003).
[CrossRef]

Other (10)

N. H. E. Weste, K. Eshraghian, Principles of CMOS VLSI Design (Addison-Wesley, 1994).

M. Horowitz, “Timing models for MOS circuits,” Ph.D. dissertation (Stanford University, 1983), http://mos.stanford.edu/papers/mh_thesis.pdf .

T. Yin, A. Apsel, A. M. Pappu, C. Reungsinpinya, A. Khimani, “Optical interconnects in commercial BiCMOS,” in Optoelectronic Integration in Silicon, D. J. Robbins, G. E. Jabbour, eds., Proc. SPIE5357, 1–10 (2004).
[CrossRef]

K. Ogata, Modern Control Engineering (Prentice-Hall, 1970).

A. J. Martin, M. Nystrom, P. Penzes, “Et2: a metric for time and energy efficiency of computation,” http://caltechcstr.library.caltech.edu/308/ , Chap. 1.

S. Wakayama, K. Gotoh, M. Saito, H. Araki, T. Shing Cheung, J. Ogawa, H. Tamura, “10-ns row cycle DRAM using temporal data storage buffer architecture,” in Digest of Technical Papers, Symposium on VLSI Circuits (IEEE, 1998), pp. 12–15.

I. Sutherland, B. Sproull, D. Harris, Logical Effort: Designing Fast CMOS Circuits (Morgan Kauffman, 1999).

W. J. Dally, J. W. Poulton, Digital Systems Engineering (Cambridge University, 1998).
[CrossRef]

D. J. Heatley, “Optical receivers,” in Design of Analog–Digital VLSI Circuits for Telecommunications and Signal Processing, Y. T. Jose E. Franca, ed. (Prentice-Hall, 1994), Chap. 5.

V. M. Hietala, K. L. Lear, M. G. Armendariz, C. P. Tigges, H. Q. Hou, J. C. Zolper, “Electrical characterization and application of very high speed vertical cavity surface emitting lasers,” in IEEE MTT-S International Microwave Symposium Digest, Vol. 1 (Institute of Electrical and Electronics Engineers, 1997), pp. 355–358.

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Figures (14)

Fig. 1
Fig. 1

Electrical fanout of nine inverters corresponding to a load capacitance of approximately 45 fF, Optoelectronic system with an optical fanout of three. Each optical receiver drives a load of three inverters.

Fig. 2
Fig. 2

Electrical taper.

Fig. 3
Fig. 3

Transmitter.

Fig. 4
Fig. 4

TIA receiver with taper.

Fig. 5
Fig. 5

Link delay with TIA receivers versus load capacitance for various optical fanout N. The load capacitance is the number of inverters driven times the load capacitance of each inverter.

Fig. 6
Fig. 6

Link energy versus load capacitance for electrical and optoelectronic topologies. The optical fanout is N.

Fig. 7
Fig. 7

Normalized Eτ2 of the optoelectronic system with respect to the fully electrical system for varying load capacitances. The points on each constant load curve have been obtained for a fanout of 1, 4, 8, and 16. The Eτ2 of the optoelectronic system reduces below 1 as the fanout increases.

Fig. 8
Fig. 8

Schematic of the electrical system with optimally inserted repeaters.

Fig. 9
Fig. 9

Schematic of the optoelectronic system with optimally inserted repeaters.

Fig. 10
Fig. 10

Delay through the electrical and optoelectronic system with repeaters. The optical fanout in the optoelectronic case is four.

Fig. 11
Fig. 11

Electrical and optoelectronic system energy with the inclusion of parasitics. The short-circuit energy in the electrical case is much larger than in the optoelectronic case. Note the logarithmic scale on the y axis.

Fig. 12
Fig. 12

Electrical and optoelectronic system energy with the inclusion of parasitics and repeaters.

Fig. 13
Fig. 13

Comparison of the voltage-independent Eτ2 metric for the electrical and the optical fanout showing that the osptoelectronic system performs better for an electrical load greater than 250 minimum-sized inverters.

Fig. 14
Fig. 14

RC ladder. The time constant for the rise time at any node e can be calculated by using the single-time-constant approximation.

Equations (31)

Equations on this page are rendered with MathJax. Learn more.

τ inv = C L C IN τ 0 ,
τ taper = C L 1 τ 0 C IN + C L 2 τ 0 C L 1 + + C L τ 0 C L ( m - 1 ) ,
C L 1 C IN = C L 2 C L 1 = = C L C L ( m - 1 ) .
τ taper = m τ 0 C L C IN m = ln ( C L C IN ) τ 0 e ,
τ link = τ Tx + τ rx , load ,
τ TLA = 6.72 C L , TIA C L , TIA R f C IN + ( 1 R out + 1 R f ) ;
τ TIA , tpr = τ 0 ln ( 6.72 α C L R out τ 0 ) e .
τ TIA , tpr , f o = τ 0 ln ( 6.72 α C L R out N τ 0 ) e .
E inv , st = κ ( V d d - 2 V T ) 3 3 t in 2 t in + t op ,
E tpr , dy = V d d 2 C L 1 β ( β m + 1 - 1 β - 1 ) ,
E tpr , st = κ L β m - 1 β m - 1 ( β - 1 ) ( V d d - 2 V T ) 3 t in 6 ,
E tpr + E tpr , dy + E tpr , st .
E Tx = 2 ( I th + N Δ I ) V d d ( 2 τ link ) ,
E TIA , st = N ( V d d I TIA , L + V d d I TIA , H ) 2 τ link , TIA .
E TIA , dy = V d d 2 C L 1 β k ( β k + 1 - 1 β - 1 ) ,
E TIA , st = κ L β k - 1 β k - 1 ( β - 1 ) ( V d d - 2 V T ) 3 t in 6 .
τ el , par = τ 0 e ln ( C L + l c w C I N ) + ln ( 10 ) l r w ( C L + l c w ) 2 ,
τ el , rep = τ 0 e ln ( C L 0 + l 0 c w C IN + S R ) + 2 τ 0 N R + 2 ln ( 10 ) S R C IN l r w ,
τ TIA , rep = τ 0 e ln 6.72 α R out ( C L 0 + l 0 c w + S R C IN ) τ 0 + 2 τ 0 N R , oe + 2 ln ( 10 ) S R C IN l r w / N ,
Δ E s s = k L ( V d d - 2 V t ) 3 6 ln ( 10 ) 2 r w ( c w + C L l ) ( 2 3 l 2 ) .
Δ E s s , oe = k L ( V d d - 2 V t ) 3 6 ln ( 10 ) 2 r w ( c w + C L l ) 2 3 ( l N ) 2 .
Δ E ss , rep = k L ( l 0 ) l ( V d d - 2 V t ) 3 2 r w ( c w + C L l ) × ( 2 3 l 0 2 ) + k L ( l - l 0 ) l ( V d d - 2 V t ) 3 l 6 ln ( 10 ) 2 × r w ( c w + C L l ) l 0 2 ,
Δ E ss , rep , oe = k L ( N l 0 ) l ( V d d - 2 V t ) 3 l 6 ln ( 10 ) 2 × r w ( c w + C L l ) ( 2 3 l 0 2 ) + k L ( l - N l 0 ) l ( V d d - 2 V t ) 3 l 6 ln ( 10 ) 2 × r w ( c w + C L l ) l 0 2 ,
E inv , st = κ ( V d d - 2 V T ) 3 6 t in 2 t in + t op .
V I = c R f [ s 2 + ( p 1 + p 2 ) s + p 1 p 2 - c ] ,
p 1 = ( 1 R f ) 1 C IN , p 2 = ( 1 R out + 1 R f ) 1 C L , TIA , c = 1 R f ( 1 R f - g m ) C L , TIA C IN .
τ TIA = 6.72 C L , TIA C L , TIA R f C IN + ( 1 R out + 1 R f ) .
I Ing , L = 1 2 [ ( V d d - 2 V T ) ( 1 κ P ) 1 / 2 + ( 1 κ N 1 + κ N 2 ) 1 / 2 ] 2 .
τ e = k R k e C k ,
N R = l [ ln ( 10 ) r w ( C L / l ) + c w 2 τ 0 ] 1 / 2 ,
S R = [ τ 0 ( C L / l ) + c w C IN 2 ln ( 10 ) r w ] 1 / 2 .

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