Abstract

The architecture of a novel, multitechnology field-programmable gate array (FPGA) is introduced. Based on conventional complementary metal-oxide semiconductor VLSI technology this architecture has demonstrated the feasibility of reconfigurable and programmable hardware for prototyping photonic information processing systems. We report that this new FPGA architecture will enable the design of reconfigurable systems that incorporated technologies outside the traditional electronic domain. The smart photoreceivers monolithically integrated in the new FPGA architecture can receive optically encoded signals in parallel and process them with user programmable logic hardware.

© 2005 Optical Society of America

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  1. W. S. Carter, K. Duong, R. H. Freeman, H.-C. Hsieh, J. Y. Ja, J. E. Mahoney, L. T. Ngo, S. L. Sze, “A user programmable reconfigurable gate array,” in IEEE Custom Integrated Circuits Conference (IEEE, 1986), pp. 233–235.
  2. P. Marchal, “Field-programmable gate arrays,” Commun. ACM 42, 57–59 (1999).
    [CrossRef]
  3. J. Rose, D. Hill, “Architectural and physical design challenges for one-million gate FPGAs and beyond,” in Proceedings of the 1997 ACM Fifth International Symposium on Field-Programmable Gate Arrays (Association for Computing Machinery, 1997), pp. 129–132.
    [CrossRef]
  4. F. R. Beyette, P. J. Stanko, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, K. M. Geib, K. D. Choquette, “Demonstration and performance of a recirculating sorter based on complementary metal oxide semiconductor logic and vertical cavity surface emitting lasers,” Opt. Eng. 37, 312–319 (1998).
    [CrossRef]
  5. P. Mal, A. Chokhani, V. S. Vagheeswar, S. K. Kumar, J. F. Cantin, F. R. Beyette, “Development of a general purpose configurable architecture for smart-pixel research,” Opt. Eng. 43, 1121–1127 (2004).
    [CrossRef]
  6. S. S. Sherif, S. K. Griebel, A. Au, D. Hui, T. H. Szymanski, H. S. Hinton, “Field-programmable smart-pixel arrays: design, VLSI implementation, and applications,” Appl. Opt. 38, 838–846 (1999).
    [CrossRef]
  7. P. Mal, J. F. Cantin, F. R. Beyette, “Design and demonstration of an optical field programmable gate array,” in Wave Optics and VLSI Photonic Devices for Information Processing, P. Ambs, F. R. Beyette, eds., Proc. SPIE4435, 238–246 (2001).
    [CrossRef]
  8. J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, “Optoelectronic FPGAs,” IEEE J. Sel. Top. Quantum Electron. 5, 306–315 (1999).
    [CrossRef]
  9. P. Mal, J. F. Cantin, F. R. Beyette, “Programmable photoreceiver module for incorporation in an optical field-programmable gate array,” in Optoelectronic and Wireless Data Management, Processing, Storage, and Retrieval, R. Raymond, P. K. Srimani, R. Su, C. W. Wilmsen, eds., Proc. SPIE4534, 138–147 (2001).
    [CrossRef]
  10. G. Jing, D. B. Oerther, I. Papautsky, “Culture-based biochip for environmental monitoring,” in Microfluidics, Bio-MEMS, and Medical Microsystems II, P. Woias, I. Papautsky, eds., Proc. SPIE5345, 68–77 (2004).
    [CrossRef]
  11. O. Leistiko, P. F. Jensen, “Integrated bio/chemical microsystems employing optical detection: the clip-on,” J. Micromech. Microeng. 8, 148–150 (1998).
    [CrossRef]
  12. H. Qiao, S. Goel, A. Grundmann, J. N. McMullin, “Biochips with integrated optics and fluidics,” in Smart Materials, Structures, and Systems, S. Mohan, B. Dattaguru, S. Gopalakrishnan, eds., Proc. SPIE5062, 873–878 (2003).
    [CrossRef]
  13. Z. Zhao, D. Cui, S. Xia, Z. Cui, “An integrated biochip design and fabrication,” in Nano- and Microtechnology: Materials, Processes, Packaging, and Systems, D. K. Sood, A. P. Malshe, R. Maeda, eds., Proc. SPIE4936, 321–326 (2002).
  14. H. Eluru, A. Polaczyk, R. Chhabra, B. Kinkle, D. Oerther, I. Papautsky, “Culture-based biochips for measuring microorganisms in waster water treatment,” in Proceedings of IEEE Conference on Microtechnologies in Medicine and Biology (IEEE, 2002).
  15. P. Mal, J. F. Cantin, F. R. Beyette, “The circuit designs of an SRAM based look-up table for high performance FPGA architecture,” in Midwest Symposium on Circuits and Systems (Institute of Electrical and Electronics Engineers, 2002), Vol. 3, pp. III227–III230.
  16. P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. I. Architecture,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 191–197 (1999).
    [CrossRef]
  17. P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. Part II. Circuit design and layout,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 321–330 (1999).
    [CrossRef]
  18. For more information on the MOSIS Foundry Service go to the MOSIS Web site at http://www.mosis.org .
  19. J. M. Rabaey, Digital Integrated Circuits: a Designer Perspective (Prentice-Hall, 1996), pp. 116–119.

2004 (1)

P. Mal, A. Chokhani, V. S. Vagheeswar, S. K. Kumar, J. F. Cantin, F. R. Beyette, “Development of a general purpose configurable architecture for smart-pixel research,” Opt. Eng. 43, 1121–1127 (2004).
[CrossRef]

1999 (5)

J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, “Optoelectronic FPGAs,” IEEE J. Sel. Top. Quantum Electron. 5, 306–315 (1999).
[CrossRef]

P. Marchal, “Field-programmable gate arrays,” Commun. ACM 42, 57–59 (1999).
[CrossRef]

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. I. Architecture,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 191–197 (1999).
[CrossRef]

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. Part II. Circuit design and layout,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 321–330 (1999).
[CrossRef]

S. S. Sherif, S. K. Griebel, A. Au, D. Hui, T. H. Szymanski, H. S. Hinton, “Field-programmable smart-pixel arrays: design, VLSI implementation, and applications,” Appl. Opt. 38, 838–846 (1999).
[CrossRef]

1998 (2)

F. R. Beyette, P. J. Stanko, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, K. M. Geib, K. D. Choquette, “Demonstration and performance of a recirculating sorter based on complementary metal oxide semiconductor logic and vertical cavity surface emitting lasers,” Opt. Eng. 37, 312–319 (1998).
[CrossRef]

O. Leistiko, P. F. Jensen, “Integrated bio/chemical microsystems employing optical detection: the clip-on,” J. Micromech. Microeng. 8, 148–150 (1998).
[CrossRef]

Au, A.

Beyette, F. R.

P. Mal, A. Chokhani, V. S. Vagheeswar, S. K. Kumar, J. F. Cantin, F. R. Beyette, “Development of a general purpose configurable architecture for smart-pixel research,” Opt. Eng. 43, 1121–1127 (2004).
[CrossRef]

F. R. Beyette, P. J. Stanko, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, K. M. Geib, K. D. Choquette, “Demonstration and performance of a recirculating sorter based on complementary metal oxide semiconductor logic and vertical cavity surface emitting lasers,” Opt. Eng. 37, 312–319 (1998).
[CrossRef]

P. Mal, J. F. Cantin, F. R. Beyette, “Programmable photoreceiver module for incorporation in an optical field-programmable gate array,” in Optoelectronic and Wireless Data Management, Processing, Storage, and Retrieval, R. Raymond, P. K. Srimani, R. Su, C. W. Wilmsen, eds., Proc. SPIE4534, 138–147 (2001).
[CrossRef]

P. Mal, J. F. Cantin, F. R. Beyette, “Design and demonstration of an optical field programmable gate array,” in Wave Optics and VLSI Photonic Devices for Information Processing, P. Ambs, F. R. Beyette, eds., Proc. SPIE4435, 238–246 (2001).
[CrossRef]

P. Mal, J. F. Cantin, F. R. Beyette, “The circuit designs of an SRAM based look-up table for high performance FPGA architecture,” in Midwest Symposium on Circuits and Systems (Institute of Electrical and Electronics Engineers, 2002), Vol. 3, pp. III227–III230.

Cantin, J. F.

P. Mal, A. Chokhani, V. S. Vagheeswar, S. K. Kumar, J. F. Cantin, F. R. Beyette, “Development of a general purpose configurable architecture for smart-pixel research,” Opt. Eng. 43, 1121–1127 (2004).
[CrossRef]

P. Mal, J. F. Cantin, F. R. Beyette, “Design and demonstration of an optical field programmable gate array,” in Wave Optics and VLSI Photonic Devices for Information Processing, P. Ambs, F. R. Beyette, eds., Proc. SPIE4435, 238–246 (2001).
[CrossRef]

P. Mal, J. F. Cantin, F. R. Beyette, “The circuit designs of an SRAM based look-up table for high performance FPGA architecture,” in Midwest Symposium on Circuits and Systems (Institute of Electrical and Electronics Engineers, 2002), Vol. 3, pp. III227–III230.

P. Mal, J. F. Cantin, F. R. Beyette, “Programmable photoreceiver module for incorporation in an optical field-programmable gate array,” in Optoelectronic and Wireless Data Management, Processing, Storage, and Retrieval, R. Raymond, P. K. Srimani, R. Su, C. W. Wilmsen, eds., Proc. SPIE4534, 138–147 (2001).
[CrossRef]

Carter, W. S.

W. S. Carter, K. Duong, R. H. Freeman, H.-C. Hsieh, J. Y. Ja, J. E. Mahoney, L. T. Ngo, S. L. Sze, “A user programmable reconfigurable gate array,” in IEEE Custom Integrated Circuits Conference (IEEE, 1986), pp. 233–235.

Chhabra, R.

H. Eluru, A. Polaczyk, R. Chhabra, B. Kinkle, D. Oerther, I. Papautsky, “Culture-based biochips for measuring microorganisms in waster water treatment,” in Proceedings of IEEE Conference on Microtechnologies in Medicine and Biology (IEEE, 2002).

Chokhani, A.

P. Mal, A. Chokhani, V. S. Vagheeswar, S. K. Kumar, J. F. Cantin, F. R. Beyette, “Development of a general purpose configurable architecture for smart-pixel research,” Opt. Eng. 43, 1121–1127 (2004).
[CrossRef]

Choquette, K. D.

F. R. Beyette, P. J. Stanko, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, K. M. Geib, K. D. Choquette, “Demonstration and performance of a recirculating sorter based on complementary metal oxide semiconductor logic and vertical cavity surface emitting lasers,” Opt. Eng. 37, 312–319 (1998).
[CrossRef]

Chow, P.

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. Part II. Circuit design and layout,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 321–330 (1999).
[CrossRef]

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. I. Architecture,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 191–197 (1999).
[CrossRef]

Chung, K.

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. I. Architecture,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 191–197 (1999).
[CrossRef]

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. Part II. Circuit design and layout,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 321–330 (1999).
[CrossRef]

Cui, D.

Z. Zhao, D. Cui, S. Xia, Z. Cui, “An integrated biochip design and fabrication,” in Nano- and Microtechnology: Materials, Processes, Packaging, and Systems, D. K. Sood, A. P. Malshe, R. Maeda, eds., Proc. SPIE4936, 321–326 (2002).

Cui, Z.

Z. Zhao, D. Cui, S. Xia, Z. Cui, “An integrated biochip design and fabrication,” in Nano- and Microtechnology: Materials, Processes, Packaging, and Systems, D. K. Sood, A. P. Malshe, R. Maeda, eds., Proc. SPIE4936, 321–326 (2002).

Dambre, J.

J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, “Optoelectronic FPGAs,” IEEE J. Sel. Top. Quantum Electron. 5, 306–315 (1999).
[CrossRef]

Depreitere, J.

J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, “Optoelectronic FPGAs,” IEEE J. Sel. Top. Quantum Electron. 5, 306–315 (1999).
[CrossRef]

Duong, K.

W. S. Carter, K. Duong, R. H. Freeman, H.-C. Hsieh, J. Y. Ja, J. E. Mahoney, L. T. Ngo, S. L. Sze, “A user programmable reconfigurable gate array,” in IEEE Custom Integrated Circuits Conference (IEEE, 1986), pp. 233–235.

Eluru, H.

H. Eluru, A. Polaczyk, R. Chhabra, B. Kinkle, D. Oerther, I. Papautsky, “Culture-based biochips for measuring microorganisms in waster water treatment,” in Proceedings of IEEE Conference on Microtechnologies in Medicine and Biology (IEEE, 2002).

Feld, S. A.

F. R. Beyette, P. J. Stanko, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, K. M. Geib, K. D. Choquette, “Demonstration and performance of a recirculating sorter based on complementary metal oxide semiconductor logic and vertical cavity surface emitting lasers,” Opt. Eng. 37, 312–319 (1998).
[CrossRef]

Freeman, R. H.

W. S. Carter, K. Duong, R. H. Freeman, H.-C. Hsieh, J. Y. Ja, J. E. Mahoney, L. T. Ngo, S. L. Sze, “A user programmable reconfigurable gate array,” in IEEE Custom Integrated Circuits Conference (IEEE, 1986), pp. 233–235.

Geib, K. M.

F. R. Beyette, P. J. Stanko, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, K. M. Geib, K. D. Choquette, “Demonstration and performance of a recirculating sorter based on complementary metal oxide semiconductor logic and vertical cavity surface emitting lasers,” Opt. Eng. 37, 312–319 (1998).
[CrossRef]

Goel, S.

H. Qiao, S. Goel, A. Grundmann, J. N. McMullin, “Biochips with integrated optics and fluidics,” in Smart Materials, Structures, and Systems, S. Mohan, B. Dattaguru, S. Gopalakrishnan, eds., Proc. SPIE5062, 873–878 (2003).
[CrossRef]

Griebel, S. K.

Grundmann, A.

H. Qiao, S. Goel, A. Grundmann, J. N. McMullin, “Biochips with integrated optics and fluidics,” in Smart Materials, Structures, and Systems, S. Mohan, B. Dattaguru, S. Gopalakrishnan, eds., Proc. SPIE5062, 873–878 (2003).
[CrossRef]

Hill, D.

J. Rose, D. Hill, “Architectural and physical design challenges for one-million gate FPGAs and beyond,” in Proceedings of the 1997 ACM Fifth International Symposium on Field-Programmable Gate Arrays (Association for Computing Machinery, 1997), pp. 129–132.
[CrossRef]

Hinton, H. S.

Hsieh, H.-C.

W. S. Carter, K. Duong, R. H. Freeman, H.-C. Hsieh, J. Y. Ja, J. E. Mahoney, L. T. Ngo, S. L. Sze, “A user programmable reconfigurable gate array,” in IEEE Custom Integrated Circuits Conference (IEEE, 1986), pp. 233–235.

Hui, D.

Ja, J. Y.

W. S. Carter, K. Duong, R. H. Freeman, H.-C. Hsieh, J. Y. Ja, J. E. Mahoney, L. T. Ngo, S. L. Sze, “A user programmable reconfigurable gate array,” in IEEE Custom Integrated Circuits Conference (IEEE, 1986), pp. 233–235.

Jensen, P. F.

O. Leistiko, P. F. Jensen, “Integrated bio/chemical microsystems employing optical detection: the clip-on,” J. Micromech. Microeng. 8, 148–150 (1998).
[CrossRef]

Jing, G.

G. Jing, D. B. Oerther, I. Papautsky, “Culture-based biochip for environmental monitoring,” in Microfluidics, Bio-MEMS, and Medical Microsystems II, P. Woias, I. Papautsky, eds., Proc. SPIE5345, 68–77 (2004).
[CrossRef]

Kinkle, B.

H. Eluru, A. Polaczyk, R. Chhabra, B. Kinkle, D. Oerther, I. Papautsky, “Culture-based biochips for measuring microorganisms in waster water treatment,” in Proceedings of IEEE Conference on Microtechnologies in Medicine and Biology (IEEE, 2002).

Kumar, S. K.

P. Mal, A. Chokhani, V. S. Vagheeswar, S. K. Kumar, J. F. Cantin, F. R. Beyette, “Development of a general purpose configurable architecture for smart-pixel research,” Opt. Eng. 43, 1121–1127 (2004).
[CrossRef]

Leistiko, O.

O. Leistiko, P. F. Jensen, “Integrated bio/chemical microsystems employing optical detection: the clip-on,” J. Micromech. Microeng. 8, 148–150 (1998).
[CrossRef]

Mahoney, J. E.

W. S. Carter, K. Duong, R. H. Freeman, H.-C. Hsieh, J. Y. Ja, J. E. Mahoney, L. T. Ngo, S. L. Sze, “A user programmable reconfigurable gate array,” in IEEE Custom Integrated Circuits Conference (IEEE, 1986), pp. 233–235.

Mal, P.

P. Mal, A. Chokhani, V. S. Vagheeswar, S. K. Kumar, J. F. Cantin, F. R. Beyette, “Development of a general purpose configurable architecture for smart-pixel research,” Opt. Eng. 43, 1121–1127 (2004).
[CrossRef]

P. Mal, J. F. Cantin, F. R. Beyette, “Design and demonstration of an optical field programmable gate array,” in Wave Optics and VLSI Photonic Devices for Information Processing, P. Ambs, F. R. Beyette, eds., Proc. SPIE4435, 238–246 (2001).
[CrossRef]

P. Mal, J. F. Cantin, F. R. Beyette, “The circuit designs of an SRAM based look-up table for high performance FPGA architecture,” in Midwest Symposium on Circuits and Systems (Institute of Electrical and Electronics Engineers, 2002), Vol. 3, pp. III227–III230.

P. Mal, J. F. Cantin, F. R. Beyette, “Programmable photoreceiver module for incorporation in an optical field-programmable gate array,” in Optoelectronic and Wireless Data Management, Processing, Storage, and Retrieval, R. Raymond, P. K. Srimani, R. Su, C. W. Wilmsen, eds., Proc. SPIE4534, 138–147 (2001).
[CrossRef]

Marchal, P.

P. Marchal, “Field-programmable gate arrays,” Commun. ACM 42, 57–59 (1999).
[CrossRef]

McMullin, J. N.

H. Qiao, S. Goel, A. Grundmann, J. N. McMullin, “Biochips with integrated optics and fluidics,” in Smart Materials, Structures, and Systems, S. Mohan, B. Dattaguru, S. Gopalakrishnan, eds., Proc. SPIE5062, 873–878 (2003).
[CrossRef]

Mitkas, P. A.

F. R. Beyette, P. J. Stanko, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, K. M. Geib, K. D. Choquette, “Demonstration and performance of a recirculating sorter based on complementary metal oxide semiconductor logic and vertical cavity surface emitting lasers,” Opt. Eng. 37, 312–319 (1998).
[CrossRef]

Ngo, L. T.

W. S. Carter, K. Duong, R. H. Freeman, H.-C. Hsieh, J. Y. Ja, J. E. Mahoney, L. T. Ngo, S. L. Sze, “A user programmable reconfigurable gate array,” in IEEE Custom Integrated Circuits Conference (IEEE, 1986), pp. 233–235.

Oerther, D.

H. Eluru, A. Polaczyk, R. Chhabra, B. Kinkle, D. Oerther, I. Papautsky, “Culture-based biochips for measuring microorganisms in waster water treatment,” in Proceedings of IEEE Conference on Microtechnologies in Medicine and Biology (IEEE, 2002).

Oerther, D. B.

G. Jing, D. B. Oerther, I. Papautsky, “Culture-based biochip for environmental monitoring,” in Microfluidics, Bio-MEMS, and Medical Microsystems II, P. Woias, I. Papautsky, eds., Proc. SPIE5345, 68–77 (2004).
[CrossRef]

Paez-Monzon, G.

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. Part II. Circuit design and layout,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 321–330 (1999).
[CrossRef]

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. I. Architecture,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 191–197 (1999).
[CrossRef]

Papautsky, I.

H. Eluru, A. Polaczyk, R. Chhabra, B. Kinkle, D. Oerther, I. Papautsky, “Culture-based biochips for measuring microorganisms in waster water treatment,” in Proceedings of IEEE Conference on Microtechnologies in Medicine and Biology (IEEE, 2002).

G. Jing, D. B. Oerther, I. Papautsky, “Culture-based biochip for environmental monitoring,” in Microfluidics, Bio-MEMS, and Medical Microsystems II, P. Woias, I. Papautsky, eds., Proc. SPIE5345, 68–77 (2004).
[CrossRef]

Polaczyk, A.

H. Eluru, A. Polaczyk, R. Chhabra, B. Kinkle, D. Oerther, I. Papautsky, “Culture-based biochips for measuring microorganisms in waster water treatment,” in Proceedings of IEEE Conference on Microtechnologies in Medicine and Biology (IEEE, 2002).

Qiao, H.

H. Qiao, S. Goel, A. Grundmann, J. N. McMullin, “Biochips with integrated optics and fluidics,” in Smart Materials, Structures, and Systems, S. Mohan, B. Dattaguru, S. Gopalakrishnan, eds., Proc. SPIE5062, 873–878 (2003).
[CrossRef]

Rabaey, J. M.

J. M. Rabaey, Digital Integrated Circuits: a Designer Perspective (Prentice-Hall, 1996), pp. 116–119.

Rahardja, I.

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. Part II. Circuit design and layout,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 321–330 (1999).
[CrossRef]

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. I. Architecture,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 191–197 (1999).
[CrossRef]

Rose, J.

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. I. Architecture,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 191–197 (1999).
[CrossRef]

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. Part II. Circuit design and layout,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 321–330 (1999).
[CrossRef]

J. Rose, D. Hill, “Architectural and physical design challenges for one-million gate FPGAs and beyond,” in Proceedings of the 1997 ACM Fifth International Symposium on Field-Programmable Gate Arrays (Association for Computing Machinery, 1997), pp. 129–132.
[CrossRef]

Seo, S. O.

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. I. Architecture,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 191–197 (1999).
[CrossRef]

P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja, “The design of a SRAM-based field-programmable gate array. Part II. Circuit design and layout,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7, 321–330 (1999).
[CrossRef]

Sherif, S. S.

Stanko, P. J.

F. R. Beyette, P. J. Stanko, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, K. M. Geib, K. D. Choquette, “Demonstration and performance of a recirculating sorter based on complementary metal oxide semiconductor logic and vertical cavity surface emitting lasers,” Opt. Eng. 37, 312–319 (1998).
[CrossRef]

Sze, S. L.

W. S. Carter, K. Duong, R. H. Freeman, H.-C. Hsieh, J. Y. Ja, J. E. Mahoney, L. T. Ngo, S. L. Sze, “A user programmable reconfigurable gate array,” in IEEE Custom Integrated Circuits Conference (IEEE, 1986), pp. 233–235.

Szymanski, T. H.

Vagheeswar, V. S.

P. Mal, A. Chokhani, V. S. Vagheeswar, S. K. Kumar, J. F. Cantin, F. R. Beyette, “Development of a general purpose configurable architecture for smart-pixel research,” Opt. Eng. 43, 1121–1127 (2004).
[CrossRef]

Van Campenhout, J.

J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, “Optoelectronic FPGAs,” IEEE J. Sel. Top. Quantum Electron. 5, 306–315 (1999).
[CrossRef]

Van Marck, H.

J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, “Optoelectronic FPGAs,” IEEE J. Sel. Top. Quantum Electron. 5, 306–315 (1999).
[CrossRef]

Wilmsen, C. W.

F. R. Beyette, P. J. Stanko, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, K. M. Geib, K. D. Choquette, “Demonstration and performance of a recirculating sorter based on complementary metal oxide semiconductor logic and vertical cavity surface emitting lasers,” Opt. Eng. 37, 312–319 (1998).
[CrossRef]

Xia, S.

Z. Zhao, D. Cui, S. Xia, Z. Cui, “An integrated biochip design and fabrication,” in Nano- and Microtechnology: Materials, Processes, Packaging, and Systems, D. K. Sood, A. P. Malshe, R. Maeda, eds., Proc. SPIE4936, 321–326 (2002).

Zhao, Z.

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Appl. Opt. (1)

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Figures (11)

Fig. 1
Fig. 1

Generic block diagram of a MT FPGA.

Fig. 2
Fig. 2

Floor plan of a MTLC that contains a MTB and four PLBs.

Fig. 3
Fig. 3

Logic diagram for the FPGA PLB.

Fig. 4
Fig. 4

Hard-wired connections to form an L3-4.2 connection topology among the four PLBs in the MTLC.

Fig. 5
Fig. 5

Detail architecture of a MTLC.

Fig. 6
Fig. 6

Circuit diagram for the threshold programmable photoreceiver (MTB). VDD is the 5 V power supply for the chip.

Fig. 7
Fig. 7

Input and output traces from the test inverter. Expanded regions of the timing diagram are used to measure propagation delay rise and fall times for the PLB design.

Fig. 8
Fig. 8

Implementation of a ring oscillator with two firm links and one soft link. A similar ring oscillator with one firm link and two soft links was also implemented to allow for performance comparison between the firm and the soft links.

Fig. 9
Fig. 9

(a) Output from a ring oscillator with two firm links and one soft link. (b) Output from a ring oscillator with one firm link and two soft links.

Fig. 10
Fig. 10

Logic analyzer traces showing the results of a 1-bit slice pipe-lined full adder.

Fig. 11
Fig. 11

Bar graph representation of the threshold optical power for eight sensitivity levels.

Tables (1)

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Table 1 Interconnections Assigned to Each PLB Input

Equations (1)

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t P = ( t p L H + t p H L ) / 2 = ( 26 + 25 ) / 2 ns = 25.5 ns .

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