Abstract

We describe the implementation of a vision system based on a hardware neural processor. The architecture of the neural network processor has been designed to exploit the computational characteristics of electronics and the communication characteristics of optics in an optimal manner, thus it is based on an optical broadcast of input signals to a dense array of processing elements. The vision system has been built by use of a prototype implementation of a neural network processor with discrete optic and optoelectronic devices. It has been adapted to work as a Hamming classifier of the images taken with a 128 × 128 complementary metal-oxide semiconductor image sensor. Its results, performance characteristics of the image classification system, and an analysis of its scalability in size and speed, with the improvement of the optoelectronic neural processor, are presented.

© 2005 Optical Society of America

Full Article  |  PDF Article

Corrections

Marta Ruiz-Llata and Horacio Lamela-Rivera, "Image identification system based on an optical broadcast neural network processor: erratum," Appl. Opt. 45, 3781-3781 (2006)
https://www.osapublishing.org/ao/abstract.cfm?uri=ao-45-16-3781

References

  • View by:
  • |
  • |
  • |

  1. M. R. G. Meireles, P. E. M. Almeida, M. G. Simoes, “A comprehensive review for Industrial applicability of artificial neural networks,” IEEE Trans. Ind. Electron. 50, 585–601 (2003).
    [CrossRef]
  2. E. N. Malamas, E. G. M. Petrakis, M. Zervakis, L. Petit, J.-D. Legat, “A survey on industrial vision systems, applications and tools.” Image Vision Comput. 21, 171–188 (2003).
    [CrossRef]
  3. R. P. Lippmann, “An introduction to computing with neural nets,” IEEE Trans. Acoust. Speech Signal Process. ASSP-4, 4–22 (1987).
  4. M. W. Roth, “Survey of neural network technology for automatic target recognition,” IEEE Trans. Neural Netw. 1, 28–43 (1990).
    [CrossRef] [PubMed]
  5. H. J. Caulfield, J. Kinser, S. K. Rogers, “Optical neural networks,” Proc. IEEE 77, 1574–1583 (1989).
    [CrossRef]
  6. D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE 88, 728–749 (2000).
    [CrossRef]
  7. N. H. Farhat, D. Psaltis, A. Prata, E. Paek, “Optical implementation of the Hopfield model,” Appl. Opt. 24, 1469–1475 (1985).
    [CrossRef] [PubMed]
  8. S. Jutamulia, F. T. S. Yu, “Overview of hybrid optical neural networks,” Opt. Laser Technol. 28, 59–72 (1996).
    [CrossRef]
  9. G. L. Li, P. K. L. Yu, “Optical intensity modulators for digital and analog applications,” J. Lightwave Technol. 21, 2010–2030 (2003).
    [CrossRef]
  10. R. P. Webb, A. J. Waddie, K. J. Symington, M. R. Taghizadeh, J. F. Snowdon, “Optoelectronic neural-network scheduler for packet switches,” Appl. Opt. 39, 788–795 (2000).
    [CrossRef]
  11. K. J. Symington, Y. Randle, A. J. Waddie, M. R. Taghizadeh, J. F. Snowdon, “Programmable optoelectronic neural network for optimization,” Appl. Opt. 43, 866–876 (2004).
    [CrossRef] [PubMed]
  12. H. Lamela, M. Ruiz-Llata, C. Warde, “Optical broadcast interconnection neural network,” Opt. Eng. 42, 2487–2488 (2003).
    [CrossRef]
  13. H. Lamela, M. Ruiz-Llata, C. Warde, “Prototype optoelectronic neural network for artificial vision systems,” in Proceedings of the IEEE Annual Conference of the Industrial Electronic Society (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 2002).
  14. L. M. Reyneri, “On the performance of pulse and spiking neurons,” Analog Integr. Circuits Signal Process. 30, 101–119 (2002).
    [CrossRef]
  15. S. Abramson, D. Saad, E. Marom, N. Konforti, “Four-quadrant optical matrix–vector multiplication machine as a neural-network processor,” Appl. Opt. 32, 1330–1337 (1993).
    [CrossRef] [PubMed]
  16. L. Tarassenko, J. N. Tombs, J. H. Reynolds, “Neural network architectures for content-addressable memory,” IEE Proc. F 138, 33–39 (1991).
  17. R. G. Carvajal, J. Ramiriez-Angulo, J. Martinez-Heredia, “High-speed high-precision min/max circuits in CMOS technology,” Electron. Lett. 36, 697–699 (2000).
    [CrossRef]
  18. G. Chapinal, S. A. Bota, M. Moreno, J. Palacin, A. Herms, “A 128 × 128 CMOS image sensor with analog memory for synchronous image capture,” IEEE Sensors J. 2, 120–127 (2002).
    [CrossRef]
  19. D. Hammerstrom, “Neurocomputing hardware: present and future,” Artif. Intell. Rev. 7, 285–300 (1993).
    [CrossRef]
  20. M. Holler, S. Tam, H. Castro, R. Benson, “An electrically trainable artificial neural network (ETANN) with 10240 “floating gate” synapses,” in 1989 IEEE International Joint Conference on Neural Networks, Vol. 2 (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1989), pp. 191–196.
  21. D. Hammerstrom, “A VLSI architecture for high-performance, low-cost, on-chip learning,” in 1990 IEEE International Joint Conference on Neural Networks, Vol. 2 (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1990), pp. 537–544.
    [CrossRef]
  22. A. Rodriguez-Vazquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo-Meana, “ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs,” IEEE Trans. Circuits Syst. I 51, 851–863 (2004).
    [CrossRef]
  23. D. C. Hendry, A. A. Duncan, N. Lightowler, “IP core implementation of a self-organizing neural network,” IEEE Trans. Neural Netw. 14, 1085–1096 (2003).
    [CrossRef]
  24. J. Schemmel, S. Hohmann, K. Meier, F. Schürmann, “A mixed-mode analog neural network using current-steering synapses,” Analog Integr. Circuits Signal Process. 38, 233–244 (2004).
    [CrossRef]
  25. Intel Corporation, “Microprocessor quick reference guide,” http://www.intel.com/pressroom/kits/quickrefyr.htm .
  26. J. D. Meindl, “Beyond Moore’s law: the interconnect era,” Comput. Sci. Eng. 5, 20–24 (January/February2003).
    [CrossRef]
  27. J. H. Collet, F. Caignet, F. Sellaye, D. Litaize, “Performance constraints for onchip optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 425–432 (2003).
    [CrossRef]
  28. M. Ruiz-Llata, H. Lamela, M. Moreno, S. Bota, A. Hermsand, C. Warde, “Progress on the development of a compact neuroprocessor with optical interconnections,” in Proceedings of the Conference on Design of Circuits and Integrated Systems (Ciudad Real, Spain, 2003), pp. 718–722.
  29. H. Lamela, M. Ruiz-Llata, D. M. Cambre, C. Warde, “Fast prototype of the optical broadcast interconnection neural network architecture,” in Optical Information Systems II, B. Javidi, D. Psaltis, eds., Proc. SPIE5557, 247–254 (2004).
    [CrossRef]

2004 (3)

K. J. Symington, Y. Randle, A. J. Waddie, M. R. Taghizadeh, J. F. Snowdon, “Programmable optoelectronic neural network for optimization,” Appl. Opt. 43, 866–876 (2004).
[CrossRef] [PubMed]

A. Rodriguez-Vazquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo-Meana, “ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs,” IEEE Trans. Circuits Syst. I 51, 851–863 (2004).
[CrossRef]

J. Schemmel, S. Hohmann, K. Meier, F. Schürmann, “A mixed-mode analog neural network using current-steering synapses,” Analog Integr. Circuits Signal Process. 38, 233–244 (2004).
[CrossRef]

2003 (7)

J. D. Meindl, “Beyond Moore’s law: the interconnect era,” Comput. Sci. Eng. 5, 20–24 (January/February2003).
[CrossRef]

J. H. Collet, F. Caignet, F. Sellaye, D. Litaize, “Performance constraints for onchip optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 425–432 (2003).
[CrossRef]

D. C. Hendry, A. A. Duncan, N. Lightowler, “IP core implementation of a self-organizing neural network,” IEEE Trans. Neural Netw. 14, 1085–1096 (2003).
[CrossRef]

H. Lamela, M. Ruiz-Llata, C. Warde, “Optical broadcast interconnection neural network,” Opt. Eng. 42, 2487–2488 (2003).
[CrossRef]

M. R. G. Meireles, P. E. M. Almeida, M. G. Simoes, “A comprehensive review for Industrial applicability of artificial neural networks,” IEEE Trans. Ind. Electron. 50, 585–601 (2003).
[CrossRef]

E. N. Malamas, E. G. M. Petrakis, M. Zervakis, L. Petit, J.-D. Legat, “A survey on industrial vision systems, applications and tools.” Image Vision Comput. 21, 171–188 (2003).
[CrossRef]

G. L. Li, P. K. L. Yu, “Optical intensity modulators for digital and analog applications,” J. Lightwave Technol. 21, 2010–2030 (2003).
[CrossRef]

2002 (2)

L. M. Reyneri, “On the performance of pulse and spiking neurons,” Analog Integr. Circuits Signal Process. 30, 101–119 (2002).
[CrossRef]

G. Chapinal, S. A. Bota, M. Moreno, J. Palacin, A. Herms, “A 128 × 128 CMOS image sensor with analog memory for synchronous image capture,” IEEE Sensors J. 2, 120–127 (2002).
[CrossRef]

2000 (3)

R. G. Carvajal, J. Ramiriez-Angulo, J. Martinez-Heredia, “High-speed high-precision min/max circuits in CMOS technology,” Electron. Lett. 36, 697–699 (2000).
[CrossRef]

R. P. Webb, A. J. Waddie, K. J. Symington, M. R. Taghizadeh, J. F. Snowdon, “Optoelectronic neural-network scheduler for packet switches,” Appl. Opt. 39, 788–795 (2000).
[CrossRef]

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE 88, 728–749 (2000).
[CrossRef]

1996 (1)

S. Jutamulia, F. T. S. Yu, “Overview of hybrid optical neural networks,” Opt. Laser Technol. 28, 59–72 (1996).
[CrossRef]

1993 (2)

1991 (1)

L. Tarassenko, J. N. Tombs, J. H. Reynolds, “Neural network architectures for content-addressable memory,” IEE Proc. F 138, 33–39 (1991).

1990 (1)

M. W. Roth, “Survey of neural network technology for automatic target recognition,” IEEE Trans. Neural Netw. 1, 28–43 (1990).
[CrossRef] [PubMed]

1989 (1)

H. J. Caulfield, J. Kinser, S. K. Rogers, “Optical neural networks,” Proc. IEEE 77, 1574–1583 (1989).
[CrossRef]

1987 (1)

R. P. Lippmann, “An introduction to computing with neural nets,” IEEE Trans. Acoust. Speech Signal Process. ASSP-4, 4–22 (1987).

1985 (1)

Abramson, S.

Almeida, P. E. M.

M. R. G. Meireles, P. E. M. Almeida, M. G. Simoes, “A comprehensive review for Industrial applicability of artificial neural networks,” IEEE Trans. Ind. Electron. 50, 585–601 (2003).
[CrossRef]

Benson, R.

M. Holler, S. Tam, H. Castro, R. Benson, “An electrically trainable artificial neural network (ETANN) with 10240 “floating gate” synapses,” in 1989 IEEE International Joint Conference on Neural Networks, Vol. 2 (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1989), pp. 191–196.

Bota, S.

M. Ruiz-Llata, H. Lamela, M. Moreno, S. Bota, A. Hermsand, C. Warde, “Progress on the development of a compact neuroprocessor with optical interconnections,” in Proceedings of the Conference on Design of Circuits and Integrated Systems (Ciudad Real, Spain, 2003), pp. 718–722.

Bota, S. A.

G. Chapinal, S. A. Bota, M. Moreno, J. Palacin, A. Herms, “A 128 × 128 CMOS image sensor with analog memory for synchronous image capture,” IEEE Sensors J. 2, 120–127 (2002).
[CrossRef]

Caignet, F.

J. H. Collet, F. Caignet, F. Sellaye, D. Litaize, “Performance constraints for onchip optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 425–432 (2003).
[CrossRef]

Cambre, D. M.

H. Lamela, M. Ruiz-Llata, D. M. Cambre, C. Warde, “Fast prototype of the optical broadcast interconnection neural network architecture,” in Optical Information Systems II, B. Javidi, D. Psaltis, eds., Proc. SPIE5557, 247–254 (2004).
[CrossRef]

Carmona-Galán, R.

A. Rodriguez-Vazquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo-Meana, “ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs,” IEEE Trans. Circuits Syst. I 51, 851–863 (2004).
[CrossRef]

Carranza, L.

A. Rodriguez-Vazquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo-Meana, “ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs,” IEEE Trans. Circuits Syst. I 51, 851–863 (2004).
[CrossRef]

Carvajal, R. G.

R. G. Carvajal, J. Ramiriez-Angulo, J. Martinez-Heredia, “High-speed high-precision min/max circuits in CMOS technology,” Electron. Lett. 36, 697–699 (2000).
[CrossRef]

Castro, H.

M. Holler, S. Tam, H. Castro, R. Benson, “An electrically trainable artificial neural network (ETANN) with 10240 “floating gate” synapses,” in 1989 IEEE International Joint Conference on Neural Networks, Vol. 2 (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1989), pp. 191–196.

Caulfield, H. J.

H. J. Caulfield, J. Kinser, S. K. Rogers, “Optical neural networks,” Proc. IEEE 77, 1574–1583 (1989).
[CrossRef]

Chapinal, G.

G. Chapinal, S. A. Bota, M. Moreno, J. Palacin, A. Herms, “A 128 × 128 CMOS image sensor with analog memory for synchronous image capture,” IEEE Sensors J. 2, 120–127 (2002).
[CrossRef]

Collet, J. H.

J. H. Collet, F. Caignet, F. Sellaye, D. Litaize, “Performance constraints for onchip optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 425–432 (2003).
[CrossRef]

Domínguez-Castro, R.

A. Rodriguez-Vazquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo-Meana, “ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs,” IEEE Trans. Circuits Syst. I 51, 851–863 (2004).
[CrossRef]

Duncan, A. A.

D. C. Hendry, A. A. Duncan, N. Lightowler, “IP core implementation of a self-organizing neural network,” IEEE Trans. Neural Netw. 14, 1085–1096 (2003).
[CrossRef]

Espejo-Meana, S.

A. Rodriguez-Vazquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo-Meana, “ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs,” IEEE Trans. Circuits Syst. I 51, 851–863 (2004).
[CrossRef]

Farhat, N. H.

Hammerstrom, D.

D. Hammerstrom, “Neurocomputing hardware: present and future,” Artif. Intell. Rev. 7, 285–300 (1993).
[CrossRef]

D. Hammerstrom, “A VLSI architecture for high-performance, low-cost, on-chip learning,” in 1990 IEEE International Joint Conference on Neural Networks, Vol. 2 (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1990), pp. 537–544.
[CrossRef]

Hendry, D. C.

D. C. Hendry, A. A. Duncan, N. Lightowler, “IP core implementation of a self-organizing neural network,” IEEE Trans. Neural Netw. 14, 1085–1096 (2003).
[CrossRef]

Herms, A.

G. Chapinal, S. A. Bota, M. Moreno, J. Palacin, A. Herms, “A 128 × 128 CMOS image sensor with analog memory for synchronous image capture,” IEEE Sensors J. 2, 120–127 (2002).
[CrossRef]

Hermsand, A.

M. Ruiz-Llata, H. Lamela, M. Moreno, S. Bota, A. Hermsand, C. Warde, “Progress on the development of a compact neuroprocessor with optical interconnections,” in Proceedings of the Conference on Design of Circuits and Integrated Systems (Ciudad Real, Spain, 2003), pp. 718–722.

Hohmann, S.

J. Schemmel, S. Hohmann, K. Meier, F. Schürmann, “A mixed-mode analog neural network using current-steering synapses,” Analog Integr. Circuits Signal Process. 38, 233–244 (2004).
[CrossRef]

Holler, M.

M. Holler, S. Tam, H. Castro, R. Benson, “An electrically trainable artificial neural network (ETANN) with 10240 “floating gate” synapses,” in 1989 IEEE International Joint Conference on Neural Networks, Vol. 2 (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1989), pp. 191–196.

Jiménez-Garrido, F.

A. Rodriguez-Vazquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo-Meana, “ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs,” IEEE Trans. Circuits Syst. I 51, 851–863 (2004).
[CrossRef]

Jutamulia, S.

S. Jutamulia, F. T. S. Yu, “Overview of hybrid optical neural networks,” Opt. Laser Technol. 28, 59–72 (1996).
[CrossRef]

Kinser, J.

H. J. Caulfield, J. Kinser, S. K. Rogers, “Optical neural networks,” Proc. IEEE 77, 1574–1583 (1989).
[CrossRef]

Konforti, N.

Lamela, H.

H. Lamela, M. Ruiz-Llata, C. Warde, “Optical broadcast interconnection neural network,” Opt. Eng. 42, 2487–2488 (2003).
[CrossRef]

H. Lamela, M. Ruiz-Llata, C. Warde, “Prototype optoelectronic neural network for artificial vision systems,” in Proceedings of the IEEE Annual Conference of the Industrial Electronic Society (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 2002).

M. Ruiz-Llata, H. Lamela, M. Moreno, S. Bota, A. Hermsand, C. Warde, “Progress on the development of a compact neuroprocessor with optical interconnections,” in Proceedings of the Conference on Design of Circuits and Integrated Systems (Ciudad Real, Spain, 2003), pp. 718–722.

H. Lamela, M. Ruiz-Llata, D. M. Cambre, C. Warde, “Fast prototype of the optical broadcast interconnection neural network architecture,” in Optical Information Systems II, B. Javidi, D. Psaltis, eds., Proc. SPIE5557, 247–254 (2004).
[CrossRef]

Legat, J.-D.

E. N. Malamas, E. G. M. Petrakis, M. Zervakis, L. Petit, J.-D. Legat, “A survey on industrial vision systems, applications and tools.” Image Vision Comput. 21, 171–188 (2003).
[CrossRef]

Li, G. L.

Lightowler, N.

D. C. Hendry, A. A. Duncan, N. Lightowler, “IP core implementation of a self-organizing neural network,” IEEE Trans. Neural Netw. 14, 1085–1096 (2003).
[CrossRef]

Liñán-Cembrano, G.

A. Rodriguez-Vazquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo-Meana, “ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs,” IEEE Trans. Circuits Syst. I 51, 851–863 (2004).
[CrossRef]

Lippmann, R. P.

R. P. Lippmann, “An introduction to computing with neural nets,” IEEE Trans. Acoust. Speech Signal Process. ASSP-4, 4–22 (1987).

Litaize, D.

J. H. Collet, F. Caignet, F. Sellaye, D. Litaize, “Performance constraints for onchip optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 425–432 (2003).
[CrossRef]

Malamas, E. N.

E. N. Malamas, E. G. M. Petrakis, M. Zervakis, L. Petit, J.-D. Legat, “A survey on industrial vision systems, applications and tools.” Image Vision Comput. 21, 171–188 (2003).
[CrossRef]

Marom, E.

Martinez-Heredia, J.

R. G. Carvajal, J. Ramiriez-Angulo, J. Martinez-Heredia, “High-speed high-precision min/max circuits in CMOS technology,” Electron. Lett. 36, 697–699 (2000).
[CrossRef]

Meier, K.

J. Schemmel, S. Hohmann, K. Meier, F. Schürmann, “A mixed-mode analog neural network using current-steering synapses,” Analog Integr. Circuits Signal Process. 38, 233–244 (2004).
[CrossRef]

Meindl, J. D.

J. D. Meindl, “Beyond Moore’s law: the interconnect era,” Comput. Sci. Eng. 5, 20–24 (January/February2003).
[CrossRef]

Meireles, M. R. G.

M. R. G. Meireles, P. E. M. Almeida, M. G. Simoes, “A comprehensive review for Industrial applicability of artificial neural networks,” IEEE Trans. Ind. Electron. 50, 585–601 (2003).
[CrossRef]

Miller, D. A. B.

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE 88, 728–749 (2000).
[CrossRef]

Moreno, M.

G. Chapinal, S. A. Bota, M. Moreno, J. Palacin, A. Herms, “A 128 × 128 CMOS image sensor with analog memory for synchronous image capture,” IEEE Sensors J. 2, 120–127 (2002).
[CrossRef]

M. Ruiz-Llata, H. Lamela, M. Moreno, S. Bota, A. Hermsand, C. Warde, “Progress on the development of a compact neuroprocessor with optical interconnections,” in Proceedings of the Conference on Design of Circuits and Integrated Systems (Ciudad Real, Spain, 2003), pp. 718–722.

Paek, E.

Palacin, J.

G. Chapinal, S. A. Bota, M. Moreno, J. Palacin, A. Herms, “A 128 × 128 CMOS image sensor with analog memory for synchronous image capture,” IEEE Sensors J. 2, 120–127 (2002).
[CrossRef]

Petit, L.

E. N. Malamas, E. G. M. Petrakis, M. Zervakis, L. Petit, J.-D. Legat, “A survey on industrial vision systems, applications and tools.” Image Vision Comput. 21, 171–188 (2003).
[CrossRef]

Petrakis, E. G. M.

E. N. Malamas, E. G. M. Petrakis, M. Zervakis, L. Petit, J.-D. Legat, “A survey on industrial vision systems, applications and tools.” Image Vision Comput. 21, 171–188 (2003).
[CrossRef]

Prata, A.

Psaltis, D.

Ramiriez-Angulo, J.

R. G. Carvajal, J. Ramiriez-Angulo, J. Martinez-Heredia, “High-speed high-precision min/max circuits in CMOS technology,” Electron. Lett. 36, 697–699 (2000).
[CrossRef]

Randle, Y.

Reyneri, L. M.

L. M. Reyneri, “On the performance of pulse and spiking neurons,” Analog Integr. Circuits Signal Process. 30, 101–119 (2002).
[CrossRef]

Reynolds, J. H.

L. Tarassenko, J. N. Tombs, J. H. Reynolds, “Neural network architectures for content-addressable memory,” IEE Proc. F 138, 33–39 (1991).

Roca-Moreno, E.

A. Rodriguez-Vazquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo-Meana, “ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs,” IEEE Trans. Circuits Syst. I 51, 851–863 (2004).
[CrossRef]

Rodriguez-Vazquez, A.

A. Rodriguez-Vazquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo-Meana, “ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs,” IEEE Trans. Circuits Syst. I 51, 851–863 (2004).
[CrossRef]

Rogers, S. K.

H. J. Caulfield, J. Kinser, S. K. Rogers, “Optical neural networks,” Proc. IEEE 77, 1574–1583 (1989).
[CrossRef]

Roth, M. W.

M. W. Roth, “Survey of neural network technology for automatic target recognition,” IEEE Trans. Neural Netw. 1, 28–43 (1990).
[CrossRef] [PubMed]

Ruiz-Llata, M.

H. Lamela, M. Ruiz-Llata, C. Warde, “Optical broadcast interconnection neural network,” Opt. Eng. 42, 2487–2488 (2003).
[CrossRef]

H. Lamela, M. Ruiz-Llata, C. Warde, “Prototype optoelectronic neural network for artificial vision systems,” in Proceedings of the IEEE Annual Conference of the Industrial Electronic Society (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 2002).

M. Ruiz-Llata, H. Lamela, M. Moreno, S. Bota, A. Hermsand, C. Warde, “Progress on the development of a compact neuroprocessor with optical interconnections,” in Proceedings of the Conference on Design of Circuits and Integrated Systems (Ciudad Real, Spain, 2003), pp. 718–722.

H. Lamela, M. Ruiz-Llata, D. M. Cambre, C. Warde, “Fast prototype of the optical broadcast interconnection neural network architecture,” in Optical Information Systems II, B. Javidi, D. Psaltis, eds., Proc. SPIE5557, 247–254 (2004).
[CrossRef]

Saad, D.

Schemmel, J.

J. Schemmel, S. Hohmann, K. Meier, F. Schürmann, “A mixed-mode analog neural network using current-steering synapses,” Analog Integr. Circuits Signal Process. 38, 233–244 (2004).
[CrossRef]

Schürmann, F.

J. Schemmel, S. Hohmann, K. Meier, F. Schürmann, “A mixed-mode analog neural network using current-steering synapses,” Analog Integr. Circuits Signal Process. 38, 233–244 (2004).
[CrossRef]

Sellaye, F.

J. H. Collet, F. Caignet, F. Sellaye, D. Litaize, “Performance constraints for onchip optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 425–432 (2003).
[CrossRef]

Simoes, M. G.

M. R. G. Meireles, P. E. M. Almeida, M. G. Simoes, “A comprehensive review for Industrial applicability of artificial neural networks,” IEEE Trans. Ind. Electron. 50, 585–601 (2003).
[CrossRef]

Snowdon, J. F.

Symington, K. J.

Taghizadeh, M. R.

Tam, S.

M. Holler, S. Tam, H. Castro, R. Benson, “An electrically trainable artificial neural network (ETANN) with 10240 “floating gate” synapses,” in 1989 IEEE International Joint Conference on Neural Networks, Vol. 2 (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1989), pp. 191–196.

Tarassenko, L.

L. Tarassenko, J. N. Tombs, J. H. Reynolds, “Neural network architectures for content-addressable memory,” IEE Proc. F 138, 33–39 (1991).

Tombs, J. N.

L. Tarassenko, J. N. Tombs, J. H. Reynolds, “Neural network architectures for content-addressable memory,” IEE Proc. F 138, 33–39 (1991).

Waddie, A. J.

Warde, C.

H. Lamela, M. Ruiz-Llata, C. Warde, “Optical broadcast interconnection neural network,” Opt. Eng. 42, 2487–2488 (2003).
[CrossRef]

H. Lamela, M. Ruiz-Llata, C. Warde, “Prototype optoelectronic neural network for artificial vision systems,” in Proceedings of the IEEE Annual Conference of the Industrial Electronic Society (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 2002).

M. Ruiz-Llata, H. Lamela, M. Moreno, S. Bota, A. Hermsand, C. Warde, “Progress on the development of a compact neuroprocessor with optical interconnections,” in Proceedings of the Conference on Design of Circuits and Integrated Systems (Ciudad Real, Spain, 2003), pp. 718–722.

H. Lamela, M. Ruiz-Llata, D. M. Cambre, C. Warde, “Fast prototype of the optical broadcast interconnection neural network architecture,” in Optical Information Systems II, B. Javidi, D. Psaltis, eds., Proc. SPIE5557, 247–254 (2004).
[CrossRef]

Webb, R. P.

Yu, F. T. S.

S. Jutamulia, F. T. S. Yu, “Overview of hybrid optical neural networks,” Opt. Laser Technol. 28, 59–72 (1996).
[CrossRef]

Yu, P. K. L.

Zervakis, M.

E. N. Malamas, E. G. M. Petrakis, M. Zervakis, L. Petit, J.-D. Legat, “A survey on industrial vision systems, applications and tools.” Image Vision Comput. 21, 171–188 (2003).
[CrossRef]

Analog Integr. Circuits Signal Process. (2)

L. M. Reyneri, “On the performance of pulse and spiking neurons,” Analog Integr. Circuits Signal Process. 30, 101–119 (2002).
[CrossRef]

J. Schemmel, S. Hohmann, K. Meier, F. Schürmann, “A mixed-mode analog neural network using current-steering synapses,” Analog Integr. Circuits Signal Process. 38, 233–244 (2004).
[CrossRef]

Appl. Opt. (4)

Artif. Intell. Rev. (1)

D. Hammerstrom, “Neurocomputing hardware: present and future,” Artif. Intell. Rev. 7, 285–300 (1993).
[CrossRef]

Comput. Sci. Eng. (1)

J. D. Meindl, “Beyond Moore’s law: the interconnect era,” Comput. Sci. Eng. 5, 20–24 (January/February2003).
[CrossRef]

Electron. Lett. (1)

R. G. Carvajal, J. Ramiriez-Angulo, J. Martinez-Heredia, “High-speed high-precision min/max circuits in CMOS technology,” Electron. Lett. 36, 697–699 (2000).
[CrossRef]

IEE Proc. F (1)

L. Tarassenko, J. N. Tombs, J. H. Reynolds, “Neural network architectures for content-addressable memory,” IEE Proc. F 138, 33–39 (1991).

IEEE J. Sel. Top. Quantum Electron. (1)

J. H. Collet, F. Caignet, F. Sellaye, D. Litaize, “Performance constraints for onchip optical interconnects,” IEEE J. Sel. Top. Quantum Electron. 9, 425–432 (2003).
[CrossRef]

IEEE Sensors J. (1)

G. Chapinal, S. A. Bota, M. Moreno, J. Palacin, A. Herms, “A 128 × 128 CMOS image sensor with analog memory for synchronous image capture,” IEEE Sensors J. 2, 120–127 (2002).
[CrossRef]

IEEE Trans. Acoust. Speech Signal Process. (1)

R. P. Lippmann, “An introduction to computing with neural nets,” IEEE Trans. Acoust. Speech Signal Process. ASSP-4, 4–22 (1987).

IEEE Trans. Circuits Syst. I (1)

A. Rodriguez-Vazquez, G. Liñán-Cembrano, L. Carranza, E. Roca-Moreno, R. Carmona-Galán, F. Jiménez-Garrido, R. Domínguez-Castro, S. Espejo-Meana, “ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs,” IEEE Trans. Circuits Syst. I 51, 851–863 (2004).
[CrossRef]

IEEE Trans. Ind. Electron. (1)

M. R. G. Meireles, P. E. M. Almeida, M. G. Simoes, “A comprehensive review for Industrial applicability of artificial neural networks,” IEEE Trans. Ind. Electron. 50, 585–601 (2003).
[CrossRef]

IEEE Trans. Neural Netw. (2)

M. W. Roth, “Survey of neural network technology for automatic target recognition,” IEEE Trans. Neural Netw. 1, 28–43 (1990).
[CrossRef] [PubMed]

D. C. Hendry, A. A. Duncan, N. Lightowler, “IP core implementation of a self-organizing neural network,” IEEE Trans. Neural Netw. 14, 1085–1096 (2003).
[CrossRef]

Image Vision Comput. (1)

E. N. Malamas, E. G. M. Petrakis, M. Zervakis, L. Petit, J.-D. Legat, “A survey on industrial vision systems, applications and tools.” Image Vision Comput. 21, 171–188 (2003).
[CrossRef]

J. Lightwave Technol. (1)

Opt. Eng. (1)

H. Lamela, M. Ruiz-Llata, C. Warde, “Optical broadcast interconnection neural network,” Opt. Eng. 42, 2487–2488 (2003).
[CrossRef]

Opt. Laser Technol. (1)

S. Jutamulia, F. T. S. Yu, “Overview of hybrid optical neural networks,” Opt. Laser Technol. 28, 59–72 (1996).
[CrossRef]

Proc. IEEE (2)

H. J. Caulfield, J. Kinser, S. K. Rogers, “Optical neural networks,” Proc. IEEE 77, 1574–1583 (1989).
[CrossRef]

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE 88, 728–749 (2000).
[CrossRef]

Other (6)

H. Lamela, M. Ruiz-Llata, C. Warde, “Prototype optoelectronic neural network for artificial vision systems,” in Proceedings of the IEEE Annual Conference of the Industrial Electronic Society (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 2002).

Intel Corporation, “Microprocessor quick reference guide,” http://www.intel.com/pressroom/kits/quickrefyr.htm .

M. Holler, S. Tam, H. Castro, R. Benson, “An electrically trainable artificial neural network (ETANN) with 10240 “floating gate” synapses,” in 1989 IEEE International Joint Conference on Neural Networks, Vol. 2 (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1989), pp. 191–196.

D. Hammerstrom, “A VLSI architecture for high-performance, low-cost, on-chip learning,” in 1990 IEEE International Joint Conference on Neural Networks, Vol. 2 (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1990), pp. 537–544.
[CrossRef]

M. Ruiz-Llata, H. Lamela, M. Moreno, S. Bota, A. Hermsand, C. Warde, “Progress on the development of a compact neuroprocessor with optical interconnections,” in Proceedings of the Conference on Design of Circuits and Integrated Systems (Ciudad Real, Spain, 2003), pp. 718–722.

H. Lamela, M. Ruiz-Llata, D. M. Cambre, C. Warde, “Fast prototype of the optical broadcast interconnection neural network architecture,” in Optical Information Systems II, B. Javidi, D. Psaltis, eds., Proc. SPIE5557, 247–254 (2004).
[CrossRef]

Cited By

OSA participates in CrossRef's Cited-By Linking service. Citing articles from OSA journals and other participating publishers are listed here.

Alert me when this article is cited.


Figures (16)

Fig. 1
Fig. 1

Optical broadcast neural network architecture.

Fig. 2
Fig. 2

Block diagram of the optoelectronic neural network cell.

Fig. 3
Fig. 3

Basic weight up & accumulate neuron design.

Fig. 4
Fig. 4

Temporal processing of a neuron.

Fig. 5
Fig. 5

Output of one weight up & accumulate neuron for inputs of (a) 0.5, (c) 0.5, (e) 0.25; weights of (a) 0.9, (c) 0.25, (e) 0.9; (b), (d), (f) time slot spans.

Fig. 6
Fig. 6

Neuron scheme for bipolar weights.

Fig. 7
Fig. 7

Hamming classifier.

Fig. 8
Fig. 8

Optoelectronic Hamming classifier.

Fig. 9
Fig. 9

8×8 sample patterns.

Fig. 10
Fig. 10

Waveforms for (a) node 1, (b) node 2, (c) node 3, (d) node 4.

Fig. 11
Fig. 11

WTA circuit.

Fig. 12
Fig. 12

Vision system block diagram

Fig. 13
Fig. 13

(a) Reference patterns and (b) stored patterns.

Fig. 14
Fig. 14

(a) Sensor image and (b) input image.

Fig. 15
Fig. 15

Picture of the vision system.

Fig. 16
Fig. 16

Vision system results.

Tables (2)

Tables Icon

Table 1 Performance Parameters of Electronic Neural Network Chips

Tables Icon

Table 2 Comparative Performance Parameters

Equations (2)

Equations on this page are rendered with MathJax. Learn more.

Δ V C = I W ( 1 C P R Δ t ) .
Δ V C = 1 C PRT X × W ,

Metrics