Abstract

A field-programmable logic device (FPLD) with optical I/O is described. FPLD’s with optical I/O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as optical signal processing, optical image processing, and optical interconnects. Our device implements six state-of-the-art dynamically programmable logic arrays (PLA’s) on a 2 mm × 2 mm die. The devices were fabricated through the Lucent Technologies–Advanced Research Projects Agency–Consortium for Optical and Optoelectronic Technologies in Computing (Lucent/ARPA/COOP) workshop by use of 0.5-µm complementary metal-oxide semiconductor–self-electro-optic device technology and were delivered in 1998. All devices are fully functional: The electronic data paths have been verified at 200 MHz, and optical tests are pending. The device has been programmed to implement a two-stage optical switching network with six 4 × 4 crossbar switches, which can realize more than 190 × 106 unique programmable input–output permutations. The same device scaled to a 2 cm × 2 cm substrate could support as many as 4000 optical I/O and 1 Tbit/s of optical I/O bandwidth and offer fully programmable digital functionality with approximately 110,000 programmable logic gates. The proposed optoelectronic FPLD is also ideally suited to realizing dense, statically reconfigurable crossbar switches. We describe an attractive application area for such devices: a rearrangeable three-stage optical switch for a wide-area-network backbone, switching 1000 traffic streams at the OC-48 data rate and supporting several terabits of traffic.

© 2000 Optical Society of America

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  1. T. H. Szymanski, H. S. Hinton, “Architecture of a field programmable smart pixel array,” in Optics in Computing (Institute of Physics, Bristol, UK, 1995), pp. 497–500.
  2. S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the 1996 IEEE/LEOS Summer Topical Meeting (Institute of Electrical and Electronics Engineers, New York, 1996), pp. 78–79.
  3. S. S. Sherif, S. K. Griebel, A. Au, D. Hui, T. H. Szymanski, H. S. Hinton, “Field-programmable smart-pixel arrays: design, VLSI implementation, and applications,” Appl. Opt. 38, 838–846 (1999).
    [CrossRef]
  4. J. Depreitere, H. Neefe, H. van Marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Berlin, 1994), pp. 352–360.
  5. M. Ishikawa, “System architecture for integrating optoelectronic computing,” Optoelectron. Devices Technol. 9, 29–36 (1994).
  6. D. Fey, B. Kasche, C. Burkert, O. Tschäche, “Specifications for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing,” Appl. Opt. 37, 284–295 (1998).
    [CrossRef]
  7. L. Selavo, S. P. Levitan, D. M. Chiarulli, “An optically reconfigurable field programmable gate array,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 146–148.
  8. J. Mumbru, D. Psaltis, “Optically programmable gate array,” in Digest of the Topical Meeting on Optics on Computing (Optical Society of America, Washington, D.C., 1999), pp. 153–155.
  9. T. H. Szymanski, M. Saint-Laurent, V. Tyan, A. Au, B. Supmonchai, “A field programmable gate array with optical I/O,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 149–152.
  10. M. Leeser, W. Meleis, M. Vai, S. Chiricescu, P. Zavracky, “Rothko: a three-dimensional FPGA,” IEEE Design Test. Comput. 15, 16–22 (1998).
    [CrossRef]
  11. A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
    [CrossRef]
  12. N. H. E. Weste, K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed. (Addison-Wesley, Reading, Mass., 1993), pp. 250–255.
  13. Altera FPGA Data Book 1996 (Altera Corporation, 2610 Orchard Parkway, San Jose, Calif., 1995).
  14. L-Edit Layout Editor Manual, Version 5 (Tanner Research, Inc., 2650 East Foothill Boulevard, Pasadena, Calif., 1995).
  15. T. H. Szymanski, V. Tyan, “Error and flow control in terabit intelligent optical backplanes,” J. Select. Top. Quantum Electron. 5, 339–352 (1999).
    [CrossRef]
  16. M. Saint-Laurent, “Software programmable logic array,” Undergraduate honors thesis (Department of Electrical and Computer Engineering, McGill University, Montreal, Quebec, Canada, 1997).
  17. E. Karali, Digital Design Principles and Computer Architecture (Prentice-Hall, New York, 1997).
  18. T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
    [CrossRef]
  19. T. M. Slagle, K. H. Wagner, “Optical smart-pixel-based Clos crossbar switch,” Appl. Opt. 36, 8336–8351 (1997).
    [CrossRef]
  20. J. Depreitere, H. van Marck, J. Van Campenhout, “A quantitative analysis of the benefits of the use of area I/O pads in FPGA’s,” Microprocess. Microsys. 21, 89–97 (1997).
    [CrossRef]

1999 (3)

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

T. H. Szymanski, V. Tyan, “Error and flow control in terabit intelligent optical backplanes,” J. Select. Top. Quantum Electron. 5, 339–352 (1999).
[CrossRef]

S. S. Sherif, S. K. Griebel, A. Au, D. Hui, T. H. Szymanski, H. S. Hinton, “Field-programmable smart-pixel arrays: design, VLSI implementation, and applications,” Appl. Opt. 38, 838–846 (1999).
[CrossRef]

1998 (2)

D. Fey, B. Kasche, C. Burkert, O. Tschäche, “Specifications for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing,” Appl. Opt. 37, 284–295 (1998).
[CrossRef]

M. Leeser, W. Meleis, M. Vai, S. Chiricescu, P. Zavracky, “Rothko: a three-dimensional FPGA,” IEEE Design Test. Comput. 15, 16–22 (1998).
[CrossRef]

1997 (2)

J. Depreitere, H. van Marck, J. Van Campenhout, “A quantitative analysis of the benefits of the use of area I/O pads in FPGA’s,” Microprocess. Microsys. 21, 89–97 (1997).
[CrossRef]

T. M. Slagle, K. H. Wagner, “Optical smart-pixel-based Clos crossbar switch,” Appl. Opt. 36, 8336–8351 (1997).
[CrossRef]

1996 (1)

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

1994 (1)

M. Ishikawa, “System architecture for integrating optoelectronic computing,” Optoelectron. Devices Technol. 9, 29–36 (1994).

Au, A.

S. S. Sherif, S. K. Griebel, A. Au, D. Hui, T. H. Szymanski, H. S. Hinton, “Field-programmable smart-pixel arrays: design, VLSI implementation, and applications,” Appl. Opt. 38, 838–846 (1999).
[CrossRef]

T. H. Szymanski, M. Saint-Laurent, V. Tyan, A. Au, B. Supmonchai, “A field programmable gate array with optical I/O,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 149–152.

Baets, R.

J. Depreitere, H. Neefe, H. van Marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Berlin, 1994), pp. 352–360.

Burkert, C.

Chiarulli, D. M.

L. Selavo, S. P. Levitan, D. M. Chiarulli, “An optically reconfigurable field programmable gate array,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 146–148.

Chiricescu, S.

M. Leeser, W. Meleis, M. Vai, S. Chiricescu, P. Zavracky, “Rothko: a three-dimensional FPGA,” IEEE Design Test. Comput. 15, 16–22 (1998).
[CrossRef]

Chirovsky, L. M. F.

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Cunningham, J. E.

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

D’Asaro, L. A.

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Dahringer, D.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Depreitere, J.

J. Depreitere, H. van Marck, J. Van Campenhout, “A quantitative analysis of the benefits of the use of area I/O pads in FPGA’s,” Microprocess. Microsys. 21, 89–97 (1997).
[CrossRef]

J. Depreitere, H. Neefe, H. van Marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Berlin, 1994), pp. 352–360.

Dhoedt, B.

J. Depreitere, H. Neefe, H. van Marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Berlin, 1994), pp. 352–360.

Eshraghian, K.

N. H. E. Weste, K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed. (Addison-Wesley, Reading, Mass., 1993), pp. 250–255.

Fey, D.

Goossen, K. W.

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Griebel, S. K.

Hinton, H. S.

S. S. Sherif, S. K. Griebel, A. Au, D. Hui, T. H. Szymanski, H. S. Hinton, “Field-programmable smart-pixel arrays: design, VLSI implementation, and applications,” Appl. Opt. 38, 838–846 (1999).
[CrossRef]

S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the 1996 IEEE/LEOS Summer Topical Meeting (Institute of Electrical and Electronics Engineers, New York, 1996), pp. 78–79.

T. H. Szymanski, H. S. Hinton, “Architecture of a field programmable smart pixel array,” in Optics in Computing (Institute of Physics, Bristol, UK, 1995), pp. 497–500.

Hobson, W. S.

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

Hui, D.

Hui, S.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Hui, S. P.

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

Ishikawa, M.

M. Ishikawa, “System architecture for integrating optoelectronic computing,” Optoelectron. Devices Technol. 9, 29–36 (1994).

Jan, W. Y.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Karali, E.

E. Karali, Digital Design Principles and Computer Architecture (Prentice-Hall, New York, 1997).

Kasche, B.

Kossives, D.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Krishnamoorthy, A. V.

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Leeser, M.

M. Leeser, W. Meleis, M. Vai, S. Chiricescu, P. Zavracky, “Rothko: a three-dimensional FPGA,” IEEE Design Test. Comput. 15, 16–22 (1998).
[CrossRef]

Leibengath, R. E.

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

Leibenguth, R. E.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Lentine, A. L.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Levitan, S. P.

L. Selavo, S. P. Levitan, D. M. Chiarulli, “An optically reconfigurable field programmable gate array,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 146–148.

Lopata, J.

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

Meleis, W.

M. Leeser, W. Meleis, M. Vai, S. Chiricescu, P. Zavracky, “Rothko: a three-dimensional FPGA,” IEEE Design Test. Comput. 15, 16–22 (1998).
[CrossRef]

Mumbru, J.

J. Mumbru, D. Psaltis, “Optically programmable gate array,” in Digest of the Topical Meeting on Optics on Computing (Optical Society of America, Washington, D.C., 1999), pp. 153–155.

Neefe, H.

J. Depreitere, H. Neefe, H. van Marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Berlin, 1994), pp. 352–360.

Psaltis, D.

J. Mumbru, D. Psaltis, “Optically programmable gate array,” in Digest of the Topical Meeting on Optics on Computing (Optical Society of America, Washington, D.C., 1999), pp. 153–155.

Saint-Laurent, M.

M. Saint-Laurent, “Software programmable logic array,” Undergraduate honors thesis (Department of Electrical and Computer Engineering, McGill University, Montreal, Quebec, Canada, 1997).

T. H. Szymanski, M. Saint-Laurent, V. Tyan, A. Au, B. Supmonchai, “A field programmable gate array with optical I/O,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 149–152.

Selavo, L.

L. Selavo, S. P. Levitan, D. M. Chiarulli, “An optically reconfigurable field programmable gate array,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 146–148.

Sherif, S. S.

S. S. Sherif, S. K. Griebel, A. Au, D. Hui, T. H. Szymanski, H. S. Hinton, “Field-programmable smart-pixel arrays: design, VLSI implementation, and applications,” Appl. Opt. 38, 838–846 (1999).
[CrossRef]

S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the 1996 IEEE/LEOS Summer Topical Meeting (Institute of Electrical and Electronics Engineers, New York, 1996), pp. 78–79.

Slagle, T. M.

Supmonchai, B.

T. H. Szymanski, M. Saint-Laurent, V. Tyan, A. Au, B. Supmonchai, “A field programmable gate array with optical I/O,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 149–152.

Szymanski, T. H.

T. H. Szymanski, V. Tyan, “Error and flow control in terabit intelligent optical backplanes,” J. Select. Top. Quantum Electron. 5, 339–352 (1999).
[CrossRef]

S. S. Sherif, S. K. Griebel, A. Au, D. Hui, T. H. Szymanski, H. S. Hinton, “Field-programmable smart-pixel arrays: design, VLSI implementation, and applications,” Appl. Opt. 38, 838–846 (1999).
[CrossRef]

T. H. Szymanski, M. Saint-Laurent, V. Tyan, A. Au, B. Supmonchai, “A field programmable gate array with optical I/O,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 149–152.

S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the 1996 IEEE/LEOS Summer Topical Meeting (Institute of Electrical and Electronics Engineers, New York, 1996), pp. 78–79.

T. H. Szymanski, H. S. Hinton, “Architecture of a field programmable smart pixel array,” in Optics in Computing (Institute of Physics, Bristol, UK, 1995), pp. 497–500.

Thienpont, H.

J. Depreitere, H. Neefe, H. van Marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Berlin, 1994), pp. 352–360.

Tschäche, O.

Tseng, B.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Tseng, B. J.

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

Tyan, V.

T. H. Szymanski, V. Tyan, “Error and flow control in terabit intelligent optical backplanes,” J. Select. Top. Quantum Electron. 5, 339–352 (1999).
[CrossRef]

T. H. Szymanski, M. Saint-Laurent, V. Tyan, A. Au, B. Supmonchai, “A field programmable gate array with optical I/O,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 149–152.

Vai, M.

M. Leeser, W. Meleis, M. Vai, S. Chiricescu, P. Zavracky, “Rothko: a three-dimensional FPGA,” IEEE Design Test. Comput. 15, 16–22 (1998).
[CrossRef]

Van Campenhout, J.

J. Depreitere, H. van Marck, J. Van Campenhout, “A quantitative analysis of the benefits of the use of area I/O pads in FPGA’s,” Microprocess. Microsys. 21, 89–97 (1997).
[CrossRef]

J. Depreitere, H. Neefe, H. van Marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Berlin, 1994), pp. 352–360.

van Marck, H.

J. Depreitere, H. van Marck, J. Van Campenhout, “A quantitative analysis of the benefits of the use of area I/O pads in FPGA’s,” Microprocess. Microsys. 21, 89–97 (1997).
[CrossRef]

J. Depreitere, H. Neefe, H. van Marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Berlin, 1994), pp. 352–360.

Veretennicoff, I.

J. Depreitere, H. Neefe, H. van Marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Berlin, 1994), pp. 352–360.

Wagner, K. H.

Walker, J. A.

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Weste, N. H. E.

N. H. E. Weste, K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed. (Addison-Wesley, Reading, Mass., 1993), pp. 250–255.

Woodward, T. K.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Wynn, J. D.

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

Zavracky, P.

M. Leeser, W. Meleis, M. Vai, S. Chiricescu, P. Zavracky, “Rothko: a three-dimensional FPGA,” IEEE Design Test. Comput. 15, 16–22 (1998).
[CrossRef]

Zydzik, G. J.

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

Appl. Opt. (3)

IEEE Design Test. Comput. (1)

M. Leeser, W. Meleis, M. Vai, S. Chiricescu, P. Zavracky, “Rothko: a three-dimensional FPGA,” IEEE Design Test. Comput. 15, 16–22 (1998).
[CrossRef]

IEEE Photon. Technol. Lett. (2)

A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E. Leibengath, S. P. Hui, G. J. Zydzik, K. W. Goossen, J. D. Wynn, B. J. Tseng, J. Lopata, J. A. Walker, J. E. Cunningham, L. A. D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits,” IEEE Photon. Technol. Lett. 11, 128–130 (1999).
[CrossRef]

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, S. Hui, B. Tseng, D. Kossives, D. Dahringer, R. E. Leibenguth, “1 Gb/s two-beam transimpedance smart-pixel optical receiver mode from hybrid GaAs MQW modulators bonded to 0.8-µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

J. Select. Top. Quantum Electron. (1)

T. H. Szymanski, V. Tyan, “Error and flow control in terabit intelligent optical backplanes,” J. Select. Top. Quantum Electron. 5, 339–352 (1999).
[CrossRef]

Microprocess. Microsys. (1)

J. Depreitere, H. van Marck, J. Van Campenhout, “A quantitative analysis of the benefits of the use of area I/O pads in FPGA’s,” Microprocess. Microsys. 21, 89–97 (1997).
[CrossRef]

Optoelectron. Devices Technol. (1)

M. Ishikawa, “System architecture for integrating optoelectronic computing,” Optoelectron. Devices Technol. 9, 29–36 (1994).

Other (11)

T. H. Szymanski, H. S. Hinton, “Architecture of a field programmable smart pixel array,” in Optics in Computing (Institute of Physics, Bristol, UK, 1995), pp. 497–500.

S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the 1996 IEEE/LEOS Summer Topical Meeting (Institute of Electrical and Electronics Engineers, New York, 1996), pp. 78–79.

J. Depreitere, H. Neefe, H. van Marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Berlin, 1994), pp. 352–360.

M. Saint-Laurent, “Software programmable logic array,” Undergraduate honors thesis (Department of Electrical and Computer Engineering, McGill University, Montreal, Quebec, Canada, 1997).

E. Karali, Digital Design Principles and Computer Architecture (Prentice-Hall, New York, 1997).

L. Selavo, S. P. Levitan, D. M. Chiarulli, “An optically reconfigurable field programmable gate array,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 146–148.

J. Mumbru, D. Psaltis, “Optically programmable gate array,” in Digest of the Topical Meeting on Optics on Computing (Optical Society of America, Washington, D.C., 1999), pp. 153–155.

T. H. Szymanski, M. Saint-Laurent, V. Tyan, A. Au, B. Supmonchai, “A field programmable gate array with optical I/O,” in Digest of the Topical Meeting on Optics in Computing (Optical Society of America, Washington, D.C., 1999), pp. 149–152.

N. H. E. Weste, K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed. (Addison-Wesley, Reading, Mass., 1993), pp. 250–255.

Altera FPGA Data Book 1996 (Altera Corporation, 2610 Orchard Parkway, San Jose, Calif., 1995).

L-Edit Layout Editor Manual, Version 5 (Tanner Research, Inc., 2650 East Foothill Boulevard, Pasadena, Calif., 1995).

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Figures (9)

Fig. 1
Fig. 1

One FSM implementation of a FPLD combination logic block. Logic functions within the FSM are dynamically programmable. Connections between neighboring FSM’s are also dynamically programmable. N, north; S, south; E, east; W, west.

Fig. 2
Fig. 2

(a) PLA with an and array followed by an or array with vertical inputs x 0, … , x M-1, several horizontal product terms z 0, … , z 9, and outputs y 0, … , y 1. (b) Logic diagram of an individual nor array with vertical inputs x 0, … , x M-1 and with horizontal outputs y 0, … , y N-1.

Fig. 3
Fig. 3

(a) Five-transistor CMOS SRAM cell used to store one personality bit. (b) Programmable cross-point at every intersection of an input x i and an output y i in the nor array. (c) Dynamically programmable nor gate with programmable inputs X 0, … , X M and one output (product) term Z i . Each nor gate is a single row of the nor array shown in Fig. 2(c).

Fig. 4
Fig. 4

(a) VLSI realization of one PLA (300 µm × 400 µm) with five inputs x 0, … , x 4, 10 product terms, and six outputs y 0, … , y 5. (b) Photograph of the 2 mm × 2 mm die with six PLA’s.

Fig. 5
Fig. 5

(a) PCB used to mount the optoelectronic FPLD for testing. (b) Oscilloscope trace of the test results. The low-amplitude waveform is the 200-MHz optical clock. The first rising edge is the logical input; the second rising edge is the FPLD output.

Fig. 6
Fig. 6

Optoelectronic FPLD programmed to implement two stages of a three-stage Clos network. NC, not connected.

Fig. 7
Fig. 7

Optical testing setup.

Fig. 8
Fig. 8

WAN optoelectronic packet switch based on an optical three-stage Clos network. MUX, multiplexer; DEMUX, demultiplexer; Gbps, gigabits/second.

Fig. 9
Fig. 9

Optical packet switch with 1024 channels for a WAN that uses a three-stage Clos network that is realized with three optoelectronic FPLD’s.

Equations (6)

Equations on this page are rendered with MathJax. Learn more.

y0yN-1=p0,0p0,M-1pN-1,0pN-1,M-1x0xM-1¯,yi=pi,0x0+pi,1x1++pi,M-1xM-1¯,
pi,j=1if yi depends on xj0otherwise.
Y=P2·P1·X¯¯.
Cy=cl=0.056 fF/μm18.7 μm/cell2M cells=2M1.05 fF.
Cx=cl=0.090 fF/μm12.2 μm/cellN cells=N1.10 fF.
Cy=cl+NCds=cN×width+NCds,Cx=cl+2MCgs=c2M×height+2MCgs,

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