Abstract

The relevance of introducing optical interconnects (OI’s) in monoprocessors and multiprocessors is studied from an architectural point of view. We show that perhaps the major explanation for why optical technologies have nearly been unable to penetrate into computers is that OI’s generally do not shorten the memory-access time, which is the most critical issue for today’s stored-program machines. In monoprocessors the memory-access time is dominated by the electronic latency of the memory itself. Thus implementing OI’s inside the memory hierarchy without changing the memory architecture cannot dramatically improve the global performance. In strongly coupled multiprocessors the node-bypass latency dominates. Therefore the higher the connectivity (possibly with optics), the shorter the path to another node, but the more expensive the network and the more complex the structure of electronic nodes. This relation leaves the choice of the best network open in terms of simplicity and latency reduction. The bottlenecks resulting from and the benefits of implementing OI’s are discussed with respect to symmetric multiprocessors, rings, and distributed shared-memory supercomputers.

© 2000 Optical Society of America

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1999 (2)

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

O. Kibar, D. A. Van Blerkom, C. Fan, S. Esener, “Power minimization and technology comparisons for digital free-space optoelectronic interconnections,” J. Lightwave Technol. 17, 546–555 (1999).
[CrossRef]

1998 (4)

Y.-S. Liu, B. Robertson, G. C. Boisset, M. H. Ayliffe, R. Iyer, D. V. Plant, “Design, implementation, and characterization of a hybrid optical interconnect for a four-stage free-space optical backplane demonstrator,” Appl. Opt. 37, 2895–2914 (1998).
[CrossRef]

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
[CrossRef]

A. Louri, B. Weech, C. Neocleous, “A spanning multichannel linked hypercube: a gradually scalable optical interconnection network for massively parallel processing,” IEEE Trans. Parallel Distribut. Sys. 9, 497–512 (1998).
[CrossRef]

A. Charlesworth, “Starfire: extending the SMP envelope,” IEEE Micro. 1, 39–49 (1998).
[CrossRef]

1997 (3)

D. A. B. Miller, “Physical reasons for optical interconnection,” Int. J. Optoelectron. 11, 155–168 (1997).

D. A. B. Miller, H. M. Ozaktas, “Limit to the bit-rate capacity of electrical interconnects from the aspect ratio of system architecture, in the Special Issue on Parallel Computing with Optical Interconnects,” J. Parallel Distribut. Comput. 41, 42–52 (1997).
[CrossRef]

R. G. Rozier, F. E. Kiamilev, A. V. Krishnamoorthy, “Design and evaluation of a photonic FFT processor,” J. Parallel Distribut. Comput. 41, 131–136 (1997).
[CrossRef]

1996 (4)

A. V. Krishnamoorthy, D. A. B. Miller, “Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Select. Top. Quantum Electron. 2, 55–76 (1996).
[CrossRef]

M. P. Y. Desmulliez, F. A. P. Tooley, J. A. B. Dines, N. L. Grant, D. J. Goodwill, D. Baillie, B. S. Wherrett, P. M. Foulk, S. Ashcroft, P. Black, “Perfect-shuffle interconnected bitonic sorter: optoelectronic design,” Appl. Opt. 34, 5077–5090 (1996).
[CrossRef]

J. C. Rodier, P. Chavel, A. Dupret, E. Belhaire, P. Garda, D. Prevost, P. Lalanne, “Video-rate simulated annealing for stochastic artificial retinas,” Opt. Commun. 132, 427–431 (1996).
[CrossRef]

A. Bolychevsky, C. R. Jesshope, V. B. Muchnick, “Dynamic scheduling in RISC architectures,” IEEE Proc. Comput. Digital Technol. 143, 309–317 (1996).
[CrossRef]

1995 (2)

N. Boden, D. Cohen, R. E. Felderman, A. E. Kulawik, C. L. Seitz, J. N. Seizovic, W.-K. Su, “Myrinet: a gigabit-per-second local area network,” IEEE Micro. 15, 29–38 (1995).
[CrossRef]

A. M. Weiner, “Femtosecond optical pulse shaping and processing,” Prog. Quantum Electron. 19, 161–237 (1995).
[CrossRef]

1991 (1)

Z. G. Vranesic, M. Stumm, D. M. Lewis, R. White, “Hector: a hierarchically structured shared-memory multiprocessor,” Computer 24, 72–79 (1991).
[CrossRef]

1988 (1)

Ashcroft, S.

Ayliffe, M. H.

Baets, R.

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

Baillie, D.

Barroso, L. A.

L. A. Barroso, M. Dubois, “The performance of cache coherent ring-based multiprocessors,” (Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, Calif., 1992).

Baukens, V.

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
[CrossRef]

Belhaire, E.

J. C. Rodier, P. Chavel, A. Dupret, E. Belhaire, P. Garda, D. Prevost, P. Lalanne, “Video-rate simulated annealing for stochastic artificial retinas,” Opt. Commun. 132, 427–431 (1996).
[CrossRef]

Black, P.

Bockstaele, R.

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

Boden, N.

N. Boden, D. Cohen, R. E. Felderman, A. E. Kulawik, C. L. Seitz, J. N. Seizovic, W.-K. Su, “Myrinet: a gigabit-per-second local area network,” IEEE Micro. 15, 29–38 (1995).
[CrossRef]

Boisset, G. C.

Bolychevsky, A.

A. Bolychevsky, C. R. Jesshope, V. B. Muchnick, “Dynamic scheduling in RISC architectures,” IEEE Proc. Comput. Digital Technol. 143, 309–317 (1996).
[CrossRef]

Borghs, S.

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
[CrossRef]

Bristow, J.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
[CrossRef]

Buczynski, R.

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
[CrossRef]

Campbell, J. C.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
[CrossRef]

Cekleov, M.

P. Sindhu, J. M. Frailong, J. Gastinel, M. Cekleov, L. Yuan, B. Gunning, D. Curry, “XDBus: a high-performance, consistent, packet-switched VLSI bus,” in Technical Digest of the Spring ’93 Computer Conferences (CompCon) (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 338–344.
[CrossRef]

Charlesworth, A.

A. Charlesworth, “Starfire: extending the SMP envelope,” IEEE Micro. 1, 39–49 (1998).
[CrossRef]

Chavel, P.

J. C. Rodier, P. Chavel, A. Dupret, E. Belhaire, P. Garda, D. Prevost, P. Lalanne, “Video-rate simulated annealing for stochastic artificial retinas,” Opt. Commun. 132, 427–431 (1996).
[CrossRef]

Chen, R. T.

S. Tang, T. Li, F. Li, L. Wu, M. Dubinovski, R. Wickman, R. T. Chen, “A 1-GHz clock signal distribution for multiprocessor supercomputers,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI96) (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 186–191.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
[CrossRef]

Cohen, D.

N. Boden, D. Cohen, R. E. Felderman, A. E. Kulawik, C. L. Seitz, J. N. Seizovic, W.-K. Su, “Myrinet: a gigabit-per-second local area network,” IEEE Micro. 15, 29–38 (1995).
[CrossRef]

Collet, J. H.

J. H. Collet, L. Fesquet, “Comparison of the latency for an optical bus and several 2-D electronic topologies,” in CD-ROM of the Proceedings of the Eleventh International Parallel Processing Symposium (IPPS) (IEEE Computer Society, Los Alamitos, Calif., 1997), CD addresses X:workshpswocscollet.pdf ; X:workshpswocscollet.ps .

W. Hlayel, D. Litaize, L. Fesquet, J. H. Collet, “Optical versus electronic bus for address-transactions in future SMP architectures,” in Proceedings of the Conference on Parallel Architecture and Compilation Techniques (PACT) (IEEE Computer Society, Los Alamitos, Calif., 1998), pp. 22–29.

Coppée, D.

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
[CrossRef]

Curry, D.

P. Sindhu, J. M. Frailong, J. Gastinel, M. Cekleov, L. Yuan, B. Gunning, D. Curry, “XDBus: a high-performance, consistent, packet-switched VLSI bus,” in Technical Digest of the Spring ’93 Computer Conferences (CompCon) (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 338–344.
[CrossRef]

Davidson, H.

H. Davidson, Sun Microsystems, 901 San Antonio Road, Palo Alto, Calif. 94303 (private communication, 11March1999).

Debaes, C.

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
[CrossRef]

Desmulliez, M. P. Y.

Dhoedt, B.

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

Dines, J. A. B.

Dubinovski, M.

S. Tang, T. Li, F. Li, L. Wu, M. Dubinovski, R. Wickman, R. T. Chen, “A 1-GHz clock signal distribution for multiprocessor supercomputers,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI96) (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 186–191.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
[CrossRef]

Dubois, M.

L. A. Barroso, M. Dubois, “The performance of cache coherent ring-based multiprocessors,” (Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, Calif., 1992).

Dupret, A.

J. C. Rodier, P. Chavel, A. Dupret, E. Belhaire, P. Garda, D. Prevost, P. Lalanne, “Video-rate simulated annealing for stochastic artificial retinas,” Opt. Commun. 132, 427–431 (1996).
[CrossRef]

Esener, S.

O. Kibar, D. A. Van Blerkom, C. Fan, S. Esener, “Power minimization and technology comparisons for digital free-space optoelectronic interconnections,” J. Lightwave Technol. 17, 546–555 (1999).
[CrossRef]

G. Yayla, P. Marchand, S. Esener, “Energy and speed analysis of digital electrical and free-space optical interconnections,” in Optical Interconnections and Parallel Processing: The Interface, A. Ferreira, P. Berthome, eds. (Kluwer Academic, Dordrecht, The Netherlands, 1997), Chap. 3.

Fan, C.

Felderman, R. E.

N. Boden, D. Cohen, R. E. Felderman, A. E. Kulawik, C. L. Seitz, J. N. Seizovic, W.-K. Su, “Myrinet: a gigabit-per-second local area network,” IEEE Micro. 15, 29–38 (1995).
[CrossRef]

Fesquet, L.

J. H. Collet, L. Fesquet, “Comparison of the latency for an optical bus and several 2-D electronic topologies,” in CD-ROM of the Proceedings of the Eleventh International Parallel Processing Symposium (IPPS) (IEEE Computer Society, Los Alamitos, Calif., 1997), CD addresses X:workshpswocscollet.pdf ; X:workshpswocscollet.ps .

W. Hlayel, D. Litaize, L. Fesquet, J. H. Collet, “Optical versus electronic bus for address-transactions in future SMP architectures,” in Proceedings of the Conference on Parallel Architecture and Compilation Techniques (PACT) (IEEE Computer Society, Los Alamitos, Calif., 1998), pp. 22–29.

Foulk, P. M.

Frailong, J. M.

P. Sindhu, J. M. Frailong, J. Gastinel, M. Cekleov, L. Yuan, B. Gunning, D. Curry, “XDBus: a high-performance, consistent, packet-switched VLSI bus,” in Technical Digest of the Spring ’93 Computer Conferences (CompCon) (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 338–344.
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Garda, P.

J. C. Rodier, P. Chavel, A. Dupret, E. Belhaire, P. Garda, D. Prevost, P. Lalanne, “Video-rate simulated annealing for stochastic artificial retinas,” Opt. Commun. 132, 427–431 (1996).
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Gastinel, J.

P. Sindhu, J. M. Frailong, J. Gastinel, M. Cekleov, L. Yuan, B. Gunning, D. Curry, “XDBus: a high-performance, consistent, packet-switched VLSI bus,” in Technical Digest of the Spring ’93 Computer Conferences (CompCon) (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 338–344.
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Genoe, J.

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
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S. Scott, M. Vernon, J. R. Goodman, “Performance of the SCI ring,” in Proceedings of the Nineteenth International Symposium on Computer Architecture (Association for Computing Machinery, New York, 1992), pp. 403–414.
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Goodwill, D. J.

Grant, N. L.

Grice, D. G.

C. B. Stunkel, D. G. Shea, D. G. Grice, P. H. Hochschild, M. Tsao, “The SP-1 high performance switch,” in Proceedings of the Conference on Scalable High Performance Computing (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 150–157.

Gunning, B.

P. Sindhu, J. M. Frailong, J. Gastinel, M. Cekleov, L. Yuan, B. Gunning, D. Curry, “XDBus: a high-performance, consistent, packet-switched VLSI bus,” in Technical Digest of the Spring ’93 Computer Conferences (CompCon) (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 338–344.
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J. L. Hennesy, D. A. Patterson, “Buses connecting I/O devices to the CPU/memory,” in Computer Architecture, a Quantitative Approach, 2nd ed. (Morgan Kauffmann, Los Altos, Calif., 1996), Sec. 6.3.

Hermanne, A.

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
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Hibbs-Brenner, M.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
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Hinton, H. S.

H. S. Hinton, An Introduction to Photonic Switching Fabrics (Plenum, New York, 1993).
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Hlayel, W.

W. Hlayel, D. Litaize, L. Fesquet, J. H. Collet, “Optical versus electronic bus for address-transactions in future SMP architectures,” in Proceedings of the Conference on Parallel Architecture and Compilation Techniques (PACT) (IEEE Computer Society, Los Alamitos, Calif., 1998), pp. 22–29.

Hochschild, P. H.

C. B. Stunkel, D. G. Shea, D. G. Grice, P. H. Hochschild, M. Tsao, “The SP-1 high performance switch,” in Proceedings of the Conference on Scalable High Performance Computing (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 150–157.

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A. Iannucci, Multithreaded Computer Architecture—A Summary of the State of the Art (Kluwer Academic, Dordrecht, The Netherlands, 1994).
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Ichioka, Y.

Iyer, R.

Jesshope, C. R.

A. Bolychevsky, C. R. Jesshope, V. B. Muchnick, “Dynamic scheduling in RISC architectures,” IEEE Proc. Comput. Digital Technol. 143, 309–317 (1996).
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Kiamilev, F. E.

R. G. Rozier, F. E. Kiamilev, A. V. Krishnamoorthy, “Design and evaluation of a photonic FFT processor,” J. Parallel Distribut. Comput. 41, 131–136 (1997).
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Kibar, O.

Krishnamoorthy, A. V.

R. G. Rozier, F. E. Kiamilev, A. V. Krishnamoorthy, “Design and evaluation of a photonic FFT processor,” J. Parallel Distribut. Comput. 41, 131–136 (1997).
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A. V. Krishnamoorthy, D. A. B. Miller, “Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Select. Top. Quantum Electron. 2, 55–76 (1996).
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Kufner, M.

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
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Kufner, S.

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
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Kulawik, A. E.

N. Boden, D. Cohen, R. E. Felderman, A. E. Kulawik, C. L. Seitz, J. N. Seizovic, W.-K. Su, “Myrinet: a gigabit-per-second local area network,” IEEE Micro. 15, 29–38 (1995).
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Lalanne, P.

J. C. Rodier, P. Chavel, A. Dupret, E. Belhaire, P. Garda, D. Prevost, P. Lalanne, “Video-rate simulated annealing for stochastic artificial retinas,” Opt. Commun. 132, 427–431 (1996).
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Z. G. Vranesic, M. Stumm, D. M. Lewis, R. White, “Hector: a hierarchically structured shared-memory multiprocessor,” Computer 24, 72–79 (1991).
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Li, F.

S. Tang, T. Li, F. Li, L. Wu, M. Dubinovski, R. Wickman, R. T. Chen, “A 1-GHz clock signal distribution for multiprocessor supercomputers,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI96) (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 186–191.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
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Li, T.

S. Tang, T. Li, F. Li, L. Wu, M. Dubinovski, R. Wickman, R. T. Chen, “A 1-GHz clock signal distribution for multiprocessor supercomputers,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI96) (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 186–191.

Litaize, D.

W. Hlayel, D. Litaize, L. Fesquet, J. H. Collet, “Optical versus electronic bus for address-transactions in future SMP architectures,” in Proceedings of the Conference on Parallel Architecture and Compilation Techniques (PACT) (IEEE Computer Society, Los Alamitos, Calif., 1998), pp. 22–29.

Liu, Y.-L.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
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Liu, Y.-S.

Louri, A.

A. Louri, B. Weech, C. Neocleous, “A spanning multichannel linked hypercube: a gradually scalable optical interconnection network for massively parallel processing,” IEEE Trans. Parallel Distribut. Sys. 9, 497–512 (1998).
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Marchand, P.

G. Yayla, P. Marchand, S. Esener, “Energy and speed analysis of digital electrical and free-space optical interconnections,” in Optical Interconnections and Parallel Processing: The Interface, A. Ferreira, P. Berthome, eds. (Kluwer Academic, Dordrecht, The Netherlands, 1997), Chap. 3.

Miller, D. A. B.

D. A. B. Miller, H. M. Ozaktas, “Limit to the bit-rate capacity of electrical interconnects from the aspect ratio of system architecture, in the Special Issue on Parallel Computing with Optical Interconnects,” J. Parallel Distribut. Comput. 41, 42–52 (1997).
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D. A. B. Miller, “Physical reasons for optical interconnection,” Int. J. Optoelectron. 11, 155–168 (1997).

A. V. Krishnamoorthy, D. A. B. Miller, “Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Select. Top. Quantum Electron. 2, 55–76 (1996).
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Muchnick, V. B.

A. Bolychevsky, C. R. Jesshope, V. B. Muchnick, “Dynamic scheduling in RISC architectures,” IEEE Proc. Comput. Digital Technol. 143, 309–317 (1996).
[CrossRef]

Neefs, H.

H. Neefs, P. Van Heuven, J. Van Campenhout, “Latency requirements of optical interconnects at different memory hierarchy levels of a computer system,” in Optics in Computing ’98, P. Chavel, D. A. B. Miller, H. Thienpont, eds., Proc. SPIE3490, 552–555 (1998).
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Neocleous, C.

A. Louri, B. Weech, C. Neocleous, “A spanning multichannel linked hypercube: a gradually scalable optical interconnection network for massively parallel processing,” IEEE Trans. Parallel Distribut. Sys. 9, 497–512 (1998).
[CrossRef]

Nodding, C.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
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Ottevaere, H.

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
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Ozaktas, H. M.

D. A. B. Miller, H. M. Ozaktas, “Limit to the bit-rate capacity of electrical interconnects from the aspect ratio of system architecture, in the Special Issue on Parallel Computing with Optical Interconnects,” J. Parallel Distribut. Comput. 41, 42–52 (1997).
[CrossRef]

Patterson, D. A.

J. L. Hennesy, D. A. Patterson, “Buses connecting I/O devices to the CPU/memory,” in Computer Architecture, a Quantitative Approach, 2nd ed. (Morgan Kauffmann, Los Altos, Calif., 1996), Sec. 6.3.

Picor, B.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
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Plant, D. V.

Prevost, D.

J. C. Rodier, P. Chavel, A. Dupret, E. Belhaire, P. Garda, D. Prevost, P. Lalanne, “Video-rate simulated annealing for stochastic artificial retinas,” Opt. Commun. 132, 427–431 (1996).
[CrossRef]

Qi, J.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
[CrossRef]

Rattan, S.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
[CrossRef]

Robertson, B.

Rodier, J. C.

J. C. Rodier, P. Chavel, A. Dupret, E. Belhaire, P. Garda, D. Prevost, P. Lalanne, “Video-rate simulated annealing for stochastic artificial retinas,” Opt. Commun. 132, 427–431 (1996).
[CrossRef]

Rozier, R. G.

R. G. Rozier, F. E. Kiamilev, A. V. Krishnamoorthy, “Design and evaluation of a photonic FFT processor,” J. Parallel Distribut. Comput. 41, 131–136 (1997).
[CrossRef]

Schow, C. L.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
[CrossRef]

Scott, H.

T. Szymanski, H. Scott, “Design of a terabit free-space photonic backplane for parallel computing,” in Proceedings of the Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI95) (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 16–27.

Scott, S.

S. Scott, “Synchronization and communication in the T3E multiprocessor,” in Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems (Association for Computing Machinery, New York, 1996), pp. 26–36.
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S. Scott, M. Vernon, J. R. Goodman, “Performance of the SCI ring,” in Proceedings of the Nineteenth International Symposium on Computer Architecture (Association for Computing Machinery, New York, 1992), pp. 403–414.
[CrossRef]

Seitz, C. L.

N. Boden, D. Cohen, R. E. Felderman, A. E. Kulawik, C. L. Seitz, J. N. Seizovic, W.-K. Su, “Myrinet: a gigabit-per-second local area network,” IEEE Micro. 15, 29–38 (1995).
[CrossRef]

Seizovic, J. N.

N. Boden, D. Cohen, R. E. Felderman, A. E. Kulawik, C. L. Seitz, J. N. Seizovic, W.-K. Su, “Myrinet: a gigabit-per-second local area network,” IEEE Micro. 15, 29–38 (1995).
[CrossRef]

Shea, D. G.

C. B. Stunkel, D. G. Shea, D. G. Grice, P. H. Hochschild, M. Tsao, “The SP-1 high performance switch,” in Proceedings of the Conference on Scalable High Performance Computing (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 150–157.

Sindhu, P.

P. Sindhu, J. M. Frailong, J. Gastinel, M. Cekleov, L. Yuan, B. Gunning, D. Curry, “XDBus: a high-performance, consistent, packet-switched VLSI bus,” in Technical Digest of the Spring ’93 Computer Conferences (CompCon) (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 338–344.
[CrossRef]

Stumm, M.

Z. G. Vranesic, M. Stumm, D. M. Lewis, R. White, “Hector: a hierarchically structured shared-memory multiprocessor,” Computer 24, 72–79 (1991).
[CrossRef]

Stunkel, C. B.

C. B. Stunkel, D. G. Shea, D. G. Grice, P. H. Hochschild, M. Tsao, “The SP-1 high performance switch,” in Proceedings of the Conference on Scalable High Performance Computing (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 150–157.

Su, W.-K.

N. Boden, D. Cohen, R. E. Felderman, A. E. Kulawik, C. L. Seitz, J. N. Seizovic, W.-K. Su, “Myrinet: a gigabit-per-second local area network,” IEEE Micro. 15, 29–38 (1995).
[CrossRef]

Szymanski, T.

T. Szymanski, H. Scott, “Design of a terabit free-space photonic backplane for parallel computing,” in Proceedings of the Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI95) (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 16–27.

Tang, S.

S. Tang, T. Li, F. Li, L. Wu, M. Dubinovski, R. Wickman, R. T. Chen, “A 1-GHz clock signal distribution for multiprocessor supercomputers,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI96) (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 186–191.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
[CrossRef]

Tanida, J.

Thienpont, H.

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
[CrossRef]

Tooley, F. A. P.

Tsao, M.

C. B. Stunkel, D. G. Shea, D. G. Grice, P. H. Hochschild, M. Tsao, “The SP-1 high performance switch,” in Proceedings of the Conference on Scalable High Performance Computing (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 150–157.

Tuteleers, P.

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
[CrossRef]

Van Blerkom, D. A.

Van Campenhout, J.

H. Neefs, P. Van Heuven, J. Van Campenhout, “Latency requirements of optical interconnects at different memory hierarchy levels of a computer system,” in Optics in Computing ’98, P. Chavel, D. A. B. Miller, H. Thienpont, eds., Proc. SPIE3490, 552–555 (1998).
[CrossRef]

Van Heuven, P.

H. Neefs, P. Van Heuven, J. Van Campenhout, “Latency requirements of optical interconnects at different memory hierarchy levels of a computer system,” in Optics in Computing ’98, P. Chavel, D. A. B. Miller, H. Thienpont, eds., Proc. SPIE3490, 552–555 (1998).
[CrossRef]

Van Hove, A.

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

Veretennicoff, I.

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
[CrossRef]

Vernon, M.

S. Scott, M. Vernon, J. R. Goodman, “Performance of the SCI ring,” in Proceedings of the Nineteenth International Symposium on Computer Architecture (Association for Computing Machinery, New York, 1992), pp. 403–414.
[CrossRef]

Verschaffelt, G.

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
[CrossRef]

Vounckx, R.

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
[CrossRef]

Vranesic, Z. G.

Z. G. Vranesic, M. Stumm, D. M. Lewis, R. White, “Hector: a hierarchically structured shared-memory multiprocessor,” Computer 24, 72–79 (1991).
[CrossRef]

Vynck, P.

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
[CrossRef]

Wang, K. H.

K. H. Wang, Advanced Computer Architecture: Parallelism, Scalability, Programmability (McGraw-Hill, New York, 1993).

Weech, B.

A. Louri, B. Weech, C. Neocleous, “A spanning multichannel linked hypercube: a gradually scalable optical interconnection network for massively parallel processing,” IEEE Trans. Parallel Distribut. Sys. 9, 497–512 (1998).
[CrossRef]

Weiner, A. M.

A. M. Weiner, “Femtosecond optical pulse shaping and processing,” Prog. Quantum Electron. 19, 161–237 (1995).
[CrossRef]

Wherrett, B. S.

White, R.

Z. G. Vranesic, M. Stumm, D. M. Lewis, R. White, “Hector: a hierarchically structured shared-memory multiprocessor,” Computer 24, 72–79 (1991).
[CrossRef]

Wickman, R.

S. Tang, T. Li, F. Li, L. Wu, M. Dubinovski, R. Wickman, R. T. Chen, “A 1-GHz clock signal distribution for multiprocessor supercomputers,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI96) (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 186–191.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
[CrossRef]

Wu, L.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
[CrossRef]

S. Tang, T. Li, F. Li, L. Wu, M. Dubinovski, R. Wickman, R. T. Chen, “A 1-GHz clock signal distribution for multiprocessor supercomputers,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI96) (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 186–191.

Yayla, G.

G. Yayla, P. Marchand, S. Esener, “Energy and speed analysis of digital electrical and free-space optical interconnections,” in Optical Interconnections and Parallel Processing: The Interface, A. Ferreira, P. Berthome, eds. (Kluwer Academic, Dordrecht, The Netherlands, 1997), Chap. 3.

Yuan, L.

P. Sindhu, J. M. Frailong, J. Gastinel, M. Cekleov, L. Yuan, B. Gunning, D. Curry, “XDBus: a high-performance, consistent, packet-switched VLSI bus,” in Technical Digest of the Spring ’93 Computer Conferences (CompCon) (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 338–344.
[CrossRef]

Appl. Opt. (3)

Computer (1)

Z. G. Vranesic, M. Stumm, D. M. Lewis, R. White, “Hector: a hierarchically structured shared-memory multiprocessor,” Computer 24, 72–79 (1991).
[CrossRef]

IEEE J. Select. Top. Quantum Electron. (1)

A. V. Krishnamoorthy, D. A. B. Miller, “Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Select. Top. Quantum Electron. 2, 55–76 (1996).
[CrossRef]

IEEE Micro. (2)

A. Charlesworth, “Starfire: extending the SMP envelope,” IEEE Micro. 1, 39–49 (1998).
[CrossRef]

N. Boden, D. Cohen, R. E. Felderman, A. E. Kulawik, C. L. Seitz, J. N. Seizovic, W.-K. Su, “Myrinet: a gigabit-per-second local area network,” IEEE Micro. 15, 29–38 (1995).
[CrossRef]

IEEE Proc. Comput. Digital Technol. (1)

A. Bolychevsky, C. R. Jesshope, V. B. Muchnick, “Dynamic scheduling in RISC architectures,” IEEE Proc. Comput. Digital Technol. 143, 309–317 (1996).
[CrossRef]

IEEE Trans. Parallel Distribut. Sys. (1)

A. Louri, B. Weech, C. Neocleous, “A spanning multichannel linked hypercube: a gradually scalable optical interconnection network for massively parallel processing,” IEEE Trans. Parallel Distribut. Sys. 9, 497–512 (1998).
[CrossRef]

Int. J. Optoelectron. (1)

D. A. B. Miller, “Physical reasons for optical interconnection,” Int. J. Optoelectron. 11, 155–168 (1997).

J. Eur. Opt. Soc. A (1)

V. Baukens, G. Verschaffelt, P. Tuteleers, P. Vynck, H. Ottevaere, M. Kufner, S. Kufner, I. Veretennicoff, R. Bockstaele, A. Van Hove, B. Dhoedt, R. Baets, H. Thienpont, “Performance of optical multi-chip-module interconnects: comparing guided-wave and free-space pathways,” J. Eur. Opt. Soc. A 1, 255–261 (1999).

J. Lightwave Technol. (1)

J. Parallel Distribut. Comput. (2)

R. G. Rozier, F. E. Kiamilev, A. V. Krishnamoorthy, “Design and evaluation of a photonic FFT processor,” J. Parallel Distribut. Comput. 41, 131–136 (1997).
[CrossRef]

D. A. B. Miller, H. M. Ozaktas, “Limit to the bit-rate capacity of electrical interconnects from the aspect ratio of system architecture, in the Special Issue on Parallel Computing with Optical Interconnects,” J. Parallel Distribut. Comput. 41, 42–52 (1997).
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Opt. Commun. (1)

J. C. Rodier, P. Chavel, A. Dupret, E. Belhaire, P. Garda, D. Prevost, P. Lalanne, “Video-rate simulated annealing for stochastic artificial retinas,” Opt. Commun. 132, 427–431 (1996).
[CrossRef]

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G. Verschaffelt, R. Buczynski, P. Tuteleers, P. Vynck, V. Baukens, H. Ottevaere, C. Debaes, S. Kufner, M. Kufner, A. Hermanne, J. Genoe, D. Coppée, R. Vounckx, S. Borghs, I. Veretennicoff, H. Thienpont, “Demonstration of a monolithic multichannel module for multi-Gb/s intra-MCM optical interconnects,” Photon. Technol. Lett. 10, 1629–1631 (1998).
[CrossRef]

Prog. Quantum Electron. (1)

A. M. Weiner, “Femtosecond optical pulse shaping and processing,” Prog. Quantum Electron. 19, 161–237 (1995).
[CrossRef]

Other (28)

P. Sindhu, J. M. Frailong, J. Gastinel, M. Cekleov, L. Yuan, B. Gunning, D. Curry, “XDBus: a high-performance, consistent, packet-switched VLSI bus,” in Technical Digest of the Spring ’93 Computer Conferences (CompCon) (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 338–344.
[CrossRef]

P. Chavel, D. A. B. Miller, H. Thienpont, eds., Optics in Computing ’98, Proc. SPIE3490 (1998).

IEEE Computer Society, Proceedings of the Fourth International Conference on Massively Parallel Processing Using Optical Interconnects, Montreal, Quebec, Canada, 22–24 June, (IEEE Computer Society, Los Alamitos, Calif., 1997).

W. Hlayel, D. Litaize, L. Fesquet, J. H. Collet, “Optical versus electronic bus for address-transactions in future SMP architectures,” in Proceedings of the Conference on Parallel Architecture and Compilation Techniques (PACT) (IEEE Computer Society, Los Alamitos, Calif., 1998), pp. 22–29.

L. A. Barroso, M. Dubois, “The performance of cache coherent ring-based multiprocessors,” (Department of Electrical Engineering-Systems, University of Southern California, Los Angeles, Calif., 1992).

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See the URL http://www.fieldbus.org .

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See the URL http://www.interbus.com .

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C. B. Stunkel, D. G. Shea, D. G. Grice, P. H. Hochschild, M. Tsao, “The SP-1 high performance switch,” in Proceedings of the Conference on Scalable High Performance Computing (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 150–157.

See the URL http://www.ssd.intel.com .

See the URL http://www.sgi.com/origin .

For a complete document on HIPPI 6400, see the URL’s http://www.noc.lanl.gov/∼jamesh/hippi64 ; http://www.scizzl.com ; and http://www1.cem.ch/HSI/sci/sci.html .

S. Scott, M. Vernon, J. R. Goodman, “Performance of the SCI ring,” in Proceedings of the Nineteenth International Symposium on Computer Architecture (Association for Computing Machinery, New York, 1992), pp. 403–414.
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A. Iannucci, Multithreaded Computer Architecture—A Summary of the State of the Art (Kluwer Academic, Dordrecht, The Netherlands, 1994).
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H. Neefs, P. Van Heuven, J. Van Campenhout, “Latency requirements of optical interconnects at different memory hierarchy levels of a computer system,” in Optics in Computing ’98, P. Chavel, D. A. B. Miller, H. Thienpont, eds., Proc. SPIE3490, 552–555 (1998).
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H. Davidson, Sun Microsystems, 901 San Antonio Road, Palo Alto, Calif. 94303 (private communication, 11March1999).

J. H. Collet, L. Fesquet, “Comparison of the latency for an optical bus and several 2-D electronic topologies,” in CD-ROM of the Proceedings of the Eleventh International Parallel Processing Symposium (IPPS) (IEEE Computer Society, Los Alamitos, Calif., 1997), CD addresses X:workshpswocscollet.pdf ; X:workshpswocscollet.ps .

K. H. Wang, Advanced Computer Architecture: Parallelism, Scalability, Programmability (McGraw-Hill, New York, 1993).

See the URL http://www.sun.com/servers/midrange/e6500/e6500.spec.html .

See the URL http://www.rambus.com/html/documentation.html .

S. Tang, T. Li, F. Li, L. Wu, M. Dubinovski, R. Wickman, R. T. Chen, “A 1-GHz clock signal distribution for multiprocessor supercomputers,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI96) (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 186–191.

R. T. Chen, L. Wu, F. Li, S. Tang, M. Dubinovski, J. Qi, C. L. Schow, J. C. Campbell, R. Wickman, B. Picor, M. Hibbs-Brenner, J. Bristow, Y.-L. Liu, S. Rattan, C. Nodding, “Si CMOS process compatible guided-wave multi-Gbit/s optical clock signal distribution system for the Cray T-90 supercomputer,” in Proceedings of the International Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI97) (IEEE Computer Society, Los Alamitos, Calif., 1997), pp. 10–24.
[CrossRef]

T. Szymanski, H. Scott, “Design of a terabit free-space photonic backplane for parallel computing,” in Proceedings of the Conference on Massively Parallel Processing Using Optical Interconnects (MMPOI95) (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 16–27.

J. L. Hennesy, D. A. Patterson, “Buses connecting I/O devices to the CPU/memory,” in Computer Architecture, a Quantitative Approach, 2nd ed. (Morgan Kauffmann, Los Altos, Calif., 1996), Sec. 6.3.

G. Yayla, P. Marchand, S. Esener, “Energy and speed analysis of digital electrical and free-space optical interconnections,” in Optical Interconnections and Parallel Processing: The Interface, A. Ferreira, P. Berthome, eds. (Kluwer Academic, Dordrecht, The Netherlands, 1997), Chap. 3.

H. S. Hinton, An Introduction to Photonic Switching Fabrics (Plenum, New York, 1993).
[CrossRef]

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Figures (3)

Fig. 1
Fig. 1

Current PC architecture: Note the two levels of caches (L1 and L2) and the absence of the shared-memory bus, which is replaced with dedicated point-to-point connections between the logic core, the graphic processor, the DRAM controller, and the L2 cache. Note also that the number of pins in the core logic is greater than 500! AGP, accelerated graphics port; PCI, peripheral-component interface; MB, megabytes.

Fig. 2
Fig. 2

Three networks for connecting N = 27 nodes: (a) A unidirectional ring that requires that all the nodes (27) be bypassed in a RTRM. The node is a 2 × 2 switch. (b) A 3-D torus with an average RTRM of approximately 4. This second network is approximately 7 times faster in terms of the hop number than that shown in (a), but the node becomes a 7 × 7 switch. The increase in the node-bypass time depends critically on the switch design. (c) A fully interconnected network. For clarity, the connections of only two nodes are drawn. The RTRM reduces to 1 hop, but the input structure of each node becomes an N-to-1 multiplexer that must operate in the asynchronous mode to reduce the MAL.

Fig. 3
Fig. 3

Modern SMP architecture: Two address buses (Addr bus1 and Addr bus2) access the memory while preserving the coherence of the caches.

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