Abstract

A smart-pixel array is a two-dimensional array of optoelectronic devices that combine optical inputs and outputs with electronic processing circuitry. A field-programmable smart-pixel array (FP-SPA) is a smart-pixel array capable of having its electronic functionality dynamically programmed in the field. Such devices could be used in a diverse range of applications, including optical switching, optical digital signal processing, and optical image processing. We describe the design, VLSI implementation, and applications of a first-generation FP-SPA implemented with the 0.8-µm complementary metal-oxide semiconductor–self-electro-optic effect device technology made available through the Lucent Technologies–Advanced Research Projects Agency Cooperative (Lucent/ARPA/COOP) program. We report spice simulations and experimental results of two sample applications: In the first application, we configure this FP-SPA as an array of free-space optical binary switches that can be used in optical multistage networks. In the second, we configure the device as an optoelectronic transceiver for a dynamically reconfigurable free-space intelligent optical backplane called the hyperplane. We also describe the testing setup and the electrical and the optical tests that demonstrate the correct functionality of the fabricated device. Such devices have the potential to reduce significantly the need for custom design and fabrication of application-specific optoelectronic devices in the same manner that field-programmable gate arrays have largely eliminated the need for custom design and fabrication of application-specific gate arrays, except in the most demanding applications.

© 1999 Optical Society of America

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References

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  1. H. S. Hinton, “Architectural considerations for photonic switching networks,” IEEE J. Selected Areas Commun. 6, 1209–1226 (1988).
    [CrossRef]
  2. T. H. Szymanski, H. S. Hinton, “Architecture of field programmable smart pixel arrays,” in Proceedings of the International Conference on Optical Computing 94 Vol. 139 of IOP Conference Proceedings (Institute of Physics, Bristol, UK, 1995), pp. 497–500.
  3. T. H. Szymanski, “Field programmable smart pixel arrays for an intelligent optical backplane,” in Proceedings of the Fourth Canadian Workshop on Field Programmable Devices (The University of Toronto, Toronto, Canada, 1996), pp. 55–61.
  4. S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the 1996 IEEE/LEOS Summer Topical Meeting (Institute of Electrical and Electronics Engineers, New York, 1996), pp. 78–79.
  5. T. M. Pinkston, C. Kuznia, “Smart-pixel-based network interface chip,” Appl. Opt. 36, 4871–4880 (1997).
    [CrossRef] [PubMed]
  6. D. Fey, B. Kasche, C. Burkert, O. Tschäche, “Specifications for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing,” Appl. Opt. 37, 284–295 (1998).
    [CrossRef]
  7. M. Ishikawa, “System architecture for integrating optoelectronic computing,” Optoelectron. Devices Technol. 9, 29–36 (1994).
  8. J. Depreitere, H. Neefe, H. van marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Prague, 1994), pp. 352–360.
  9. K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, “GaAs MQW modulator integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
    [CrossRef]
  10. T. H. Szymanski, H. S. Hinton, “A reconfigurable intelligent optical backplane for parallel computing and communications,” Appl. Opt. 35, 1253–1268 (1996).
    [CrossRef] [PubMed]
  11. L-Edit Layout Editor Manual, Version 5, Tanner Research, Inc., 2650 East Foothill Boulevard, Pasadena, Calif. 91107 (1995).
  12. D. R. Rolston, B. Robertson, H. S. Hinton, D. V. Plant, “Analysis of a microchannel interconnect based on the clustering of smart-pixel-device windows,” Appl. Opt. 35, 1220–1233 (1996).
    [CrossRef] [PubMed]
  13. S. K. Griebel, M. Richardson, K. E. Devenport, H. S. Hinton, “Experimental performance of an ATM-based buffered hyperplane CMOS–SEED smart pixel array,” in Optoelectronic Interconnects and Packaging IV, R. T. Chen, P. S. Guilfoyle, eds., Proc. SPIE3005, 254–256 (1997).
    [CrossRef]

1998

1997

1996

1995

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, “GaAs MQW modulator integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

1994

M. Ishikawa, “System architecture for integrating optoelectronic computing,” Optoelectron. Devices Technol. 9, 29–36 (1994).

1988

H. S. Hinton, “Architectural considerations for photonic switching networks,” IEEE J. Selected Areas Commun. 6, 1209–1226 (1988).
[CrossRef]

Baets, R.

J. Depreitere, H. Neefe, H. van marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Prague, 1994), pp. 352–360.

Burkert, C.

D’Asaro, L. A.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, “GaAs MQW modulator integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Depreitere, J.

J. Depreitere, H. Neefe, H. van marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Prague, 1994), pp. 352–360.

Devenport, K. E.

S. K. Griebel, M. Richardson, K. E. Devenport, H. S. Hinton, “Experimental performance of an ATM-based buffered hyperplane CMOS–SEED smart pixel array,” in Optoelectronic Interconnects and Packaging IV, R. T. Chen, P. S. Guilfoyle, eds., Proc. SPIE3005, 254–256 (1997).
[CrossRef]

Dhoedt, B.

J. Depreitere, H. Neefe, H. van marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Prague, 1994), pp. 352–360.

Fey, D.

Goossen, K. W.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, “GaAs MQW modulator integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Griebel, S. K.

S. K. Griebel, M. Richardson, K. E. Devenport, H. S. Hinton, “Experimental performance of an ATM-based buffered hyperplane CMOS–SEED smart pixel array,” in Optoelectronic Interconnects and Packaging IV, R. T. Chen, P. S. Guilfoyle, eds., Proc. SPIE3005, 254–256 (1997).
[CrossRef]

Hinton, H. S.

D. R. Rolston, B. Robertson, H. S. Hinton, D. V. Plant, “Analysis of a microchannel interconnect based on the clustering of smart-pixel-device windows,” Appl. Opt. 35, 1220–1233 (1996).
[CrossRef] [PubMed]

T. H. Szymanski, H. S. Hinton, “A reconfigurable intelligent optical backplane for parallel computing and communications,” Appl. Opt. 35, 1253–1268 (1996).
[CrossRef] [PubMed]

H. S. Hinton, “Architectural considerations for photonic switching networks,” IEEE J. Selected Areas Commun. 6, 1209–1226 (1988).
[CrossRef]

S. K. Griebel, M. Richardson, K. E. Devenport, H. S. Hinton, “Experimental performance of an ATM-based buffered hyperplane CMOS–SEED smart pixel array,” in Optoelectronic Interconnects and Packaging IV, R. T. Chen, P. S. Guilfoyle, eds., Proc. SPIE3005, 254–256 (1997).
[CrossRef]

S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the 1996 IEEE/LEOS Summer Topical Meeting (Institute of Electrical and Electronics Engineers, New York, 1996), pp. 78–79.

T. H. Szymanski, H. S. Hinton, “Architecture of field programmable smart pixel arrays,” in Proceedings of the International Conference on Optical Computing 94 Vol. 139 of IOP Conference Proceedings (Institute of Physics, Bristol, UK, 1995), pp. 497–500.

Hui, S. P.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, “GaAs MQW modulator integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Ishikawa, M.

M. Ishikawa, “System architecture for integrating optoelectronic computing,” Optoelectron. Devices Technol. 9, 29–36 (1994).

Kasche, B.

Kuznia, C.

Neefe, H.

J. Depreitere, H. Neefe, H. van marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Prague, 1994), pp. 352–360.

Pinkston, T. M.

Plant, D. V.

Richardson, M.

S. K. Griebel, M. Richardson, K. E. Devenport, H. S. Hinton, “Experimental performance of an ATM-based buffered hyperplane CMOS–SEED smart pixel array,” in Optoelectronic Interconnects and Packaging IV, R. T. Chen, P. S. Guilfoyle, eds., Proc. SPIE3005, 254–256 (1997).
[CrossRef]

Robertson, B.

Rolston, D. R.

Sherif, S. S.

S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the 1996 IEEE/LEOS Summer Topical Meeting (Institute of Electrical and Electronics Engineers, New York, 1996), pp. 78–79.

Szymanski, T. H.

T. H. Szymanski, H. S. Hinton, “A reconfigurable intelligent optical backplane for parallel computing and communications,” Appl. Opt. 35, 1253–1268 (1996).
[CrossRef] [PubMed]

T. H. Szymanski, “Field programmable smart pixel arrays for an intelligent optical backplane,” in Proceedings of the Fourth Canadian Workshop on Field Programmable Devices (The University of Toronto, Toronto, Canada, 1996), pp. 55–61.

S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the 1996 IEEE/LEOS Summer Topical Meeting (Institute of Electrical and Electronics Engineers, New York, 1996), pp. 78–79.

T. H. Szymanski, H. S. Hinton, “Architecture of field programmable smart pixel arrays,” in Proceedings of the International Conference on Optical Computing 94 Vol. 139 of IOP Conference Proceedings (Institute of Physics, Bristol, UK, 1995), pp. 497–500.

Thienpont, H.

J. Depreitere, H. Neefe, H. van marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Prague, 1994), pp. 352–360.

Tschäche, O.

Tseng, B.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, “GaAs MQW modulator integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Van Campenhout, J.

J. Depreitere, H. Neefe, H. van marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Prague, 1994), pp. 352–360.

van marck, H.

J. Depreitere, H. Neefe, H. van marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Prague, 1994), pp. 352–360.

Veretennicoff, I.

J. Depreitere, H. Neefe, H. van marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Prague, 1994), pp. 352–360.

Walker, J. A.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, “GaAs MQW modulator integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Appl. Opt.

IEEE J. Selected Areas Commun.

H. S. Hinton, “Architectural considerations for photonic switching networks,” IEEE J. Selected Areas Commun. 6, 1209–1226 (1988).
[CrossRef]

IEEE Photon. Technol. Lett.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, “GaAs MQW modulator integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Optoelectron. Devices Technol.

M. Ishikawa, “System architecture for integrating optoelectronic computing,” Optoelectron. Devices Technol. 9, 29–36 (1994).

Other

J. Depreitere, H. Neefe, H. van marck, J. Van Campenhout, R. Baets, B. Dhoedt, H. Thienpont, I. Veretennicoff, “An optoelectronic 3D field programmable gate array,” in Proceedings of the Fourth International Workshop on Field Programmable Logic and Applications (Springer-Verlag, Prague, 1994), pp. 352–360.

L-Edit Layout Editor Manual, Version 5, Tanner Research, Inc., 2650 East Foothill Boulevard, Pasadena, Calif. 91107 (1995).

S. K. Griebel, M. Richardson, K. E. Devenport, H. S. Hinton, “Experimental performance of an ATM-based buffered hyperplane CMOS–SEED smart pixel array,” in Optoelectronic Interconnects and Packaging IV, R. T. Chen, P. S. Guilfoyle, eds., Proc. SPIE3005, 254–256 (1997).
[CrossRef]

T. H. Szymanski, H. S. Hinton, “Architecture of field programmable smart pixel arrays,” in Proceedings of the International Conference on Optical Computing 94 Vol. 139 of IOP Conference Proceedings (Institute of Physics, Bristol, UK, 1995), pp. 497–500.

T. H. Szymanski, “Field programmable smart pixel arrays for an intelligent optical backplane,” in Proceedings of the Fourth Canadian Workshop on Field Programmable Devices (The University of Toronto, Toronto, Canada, 1996), pp. 55–61.

S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the 1996 IEEE/LEOS Summer Topical Meeting (Institute of Electrical and Electronics Engineers, New York, 1996), pp. 78–79.

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Figures (12)

Fig. 1
Fig. 1

I/O ports of a single programmable pixel.

Fig. 2
Fig. 2

Finite-state machine representation of the FP-SPA.

Fig. 3
Fig. 3

Schematic of a single programmable pixel. C i,j denotes the jth control bit for the ith LUT or the eight-to-one MUX. M i denotes the control bit for the ith two-to-one MUX. Each pixel has 55 control bits.

Fig. 4
Fig. 4

Photograph of the FP-SPA VLSI die. The control RAM is at the top of the integrated circuit. The 4 × 3 array of pixels is underneath the control RAM.

Fig. 5
Fig. 5

Differential optical signaling scheme.

Fig. 6
Fig. 6

(a) Bar state of a two-input, two-output binary switch. (b) Cross state of a two-input, two-output binary switch.

Fig. 7
Fig. 7

FP-SPA configured as an optical binary switch in the bar state.

Fig. 8
Fig. 8

FP-SPA configured as an optical binary switch in the cross state.

Fig. 9
Fig. 9

FP-SPAs configured to implement the hyperplane optical backplane: (a) injection of electrical data onto one optical channel and (b) extraction of electrical data from one optical channel.

Fig. 10
Fig. 10

FP-SPA as a hyperplane: electrical data injection.

Fig. 11
Fig. 11

FP-SPA as a hyperplane: electrical data extraction and optical data regeneration.

Fig. 12
Fig. 12

Simplified optical testing setup.

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