Abstract

We present an optoelectronic-VLSI system that integrates complementary metal-oxide semiconductor/multiple-quantum-well smart pixels for high-throughput computation and signal processing. The system uses 5 × 10 cellular smart-pixel arrays with intrachip electrical mesh interconnections and interchip optical point-to-point interconnections. Each smart pixel is a fine grain microprocessor that executes binary image algebra instructions. There is one dual-rail optical modulator output and one dual-rail optical detector input in each pixel. These optical input–output arrays provide chip-to-chip optical interconnects. Cascading these smart-pixel array chips permits direct transfer of two-dimensional data or images in parallel. We present laboratory demonstrations of the system for digital image edge detection and digital video motion estimation. We also analyze the performance of the system compared with that of conventional single-instruction–multiple-data processors.

© 1999 Optical Society of America

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    [CrossRef]
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  23. A. V. Krishnamoorthy, R. G. Rozier, J. E. Ford, F. E. Kiamilev, “Demonstration of a CMOS static RAM chip with high-speed optical read and write,” in Spatial Light Modulators, G. Burdge, S. Esener, eds., Vol. 14 of OSA Trends in Optics and Photonics Series (Optical Society of America, Washington, D.C., 1997), pp. 23–26.
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1997 (1)

A. V. Krishnamoorthy, K. W. Goossen, “Progress in optoelectronic-VLSI smart pixel technology based on GaAs/AlGaAs MQW modulators,” Int. J. Optoelectron. 11, 181–198 (1997).

1996 (3)

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, “1-Gb/s two-beam transimpedance smart pixel optical receivers made from hybrid GaAs MQW modulators bonded to 0.8 µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

J. D. Allen, D. E. Schimmel, “Issues in the design of high performance SIMD architectures,” IEEE Trans. Parallel Distr. Syst. 7, 818–829 (1996).
[CrossRef]

A. Broggi, F. Gregoretti, “Performance evaluation and optimization in low-cost cellular SIMD systems,” Microprocess. Microprogramm. 41, 659–678 (1996).
[CrossRef]

1995 (5)

J. Goodenough, R. J. Meacham, J. D. Morris, N. L. Seed, P. A. Ivey, “A single chip video signal processing architecture for image processing, coding, and computer vision,” IEEE Trans. Circ. Syst. Video Technol. 5, 436–445 (1995).
[CrossRef]

S. Okazaki, Y. Fujita, N. Yamashita, “A compact real-time vision system using integrated memory array processor architecture,” IEEE Trans. Circ. Syst. Video Technol. 5, 446–452 (1995).
[CrossRef]

H. D. Santos, J. C. Ramalho, J. M. Fernandes, A. J. Proenca, “A heterogeneous computer vision architecture: implementation issues,” Comput. Syst. Eng. 6, 401–408 (1995).
[CrossRef]

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D’Asaro, S. P. Hui, B. Tseng, “3-D integration of MQW modulators over active sub-micron CMOS circuits: 375Mb/s transimpedance receiver–transmitter circuit,” IEEE Photon. Technol. Lett. 7, 1288–1290 (1995).
[CrossRef]

1994 (1)

J. M. del Rosario, A. K. Choudhary, “High-performance I/O for massively parallel computers—problems and prospects,” IEEE Comput. 27(3), 59–68 (1994).
[CrossRef]

1993 (1)

1991 (1)

D. Le Gall, “MPEG: a video compression standard for multimedia applications,” Commun. ACM 34, 46–58 (1991).
[CrossRef]

1990 (1)

P. Maragos, R. Shafer, “Morphological systems for multidimensional signal processing,” Proc. IEEE 78, 690–709 (1990).
[CrossRef]

1989 (1)

Allen, J. D.

J. D. Allen, D. E. Schimmel, “Issues in the design of high performance SIMD architectures,” IEEE Trans. Parallel Distr. Syst. 7, 818–829 (1996).
[CrossRef]

Aplin, G. F.

A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D’Asaro, S. P. Hui, B. Tseng, “3-D integration of MQW modulators over active sub-micron CMOS circuits: 375Mb/s transimpedance receiver–transmitter circuit,” IEEE Photon. Technol. Lett. 7, 1288–1290 (1995).
[CrossRef]

Bacon, D. D.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Broggi, A.

A. Broggi, F. Gregoretti, “Performance evaluation and optimization in low-cost cellular SIMD systems,” Microprocess. Microprogramm. 41, 659–678 (1996).
[CrossRef]

Chavel, P.

Chen, C.-H.

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, A. A. Sawchuk, “Integration of CMOS/MQW smart pixel array cellular logic (SPARCL) processors for SIMD parallel pipeline processing,” presented at the 1997 North American Chinese Photonics Technology Conference, Los Angeles, Calif., 17–19 October 1997.

C. B. Kuznia, J.-M. Wu, C.-H. Chen, B. Hoanca, L. Cheng, A. G. Weber, A. A. Sawchuk, “Two-dimensional parallel pipeline processing with smart pixel array cellular logic (SPARCL) processors: system implementation,” submitted to J. Lightwave Technol.

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, L. Cheng, A. G. Weber, A. A. Sawchuk, “Smart pixel array cellular logic (SPARCL) processor for eliminating SIMD I/O bottlenecks: system demonstration and performance scaling,” in Optics in Computing, Vol. 8 of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 152–154.

C. B. Kuznia, J.-M. Wu, C.-H. Chen, A. A. Sawchuk, L. Cheng, “Hybrid CMOS/SEED smart pixel array for 2D parallel pipeline operations,” in Digest IEEE/LEOS 1996 Summer Topical Meetings: Smart Pixels (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1996), pp. 80–81.
[CrossRef]

Cheng, L.

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, L. Cheng, A. G. Weber, A. A. Sawchuk, “Smart pixel array cellular logic (SPARCL) processor for eliminating SIMD I/O bottlenecks: system demonstration and performance scaling,” in Optics in Computing, Vol. 8 of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 152–154.

C. B. Kuznia, J.-M. Wu, C.-H. Chen, A. A. Sawchuk, L. Cheng, “Hybrid CMOS/SEED smart pixel array for 2D parallel pipeline operations,” in Digest IEEE/LEOS 1996 Summer Topical Meetings: Smart Pixels (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1996), pp. 80–81.
[CrossRef]

C. B. Kuznia, J.-M. Wu, C.-H. Chen, B. Hoanca, L. Cheng, A. G. Weber, A. A. Sawchuk, “Two-dimensional parallel pipeline processing with smart pixel array cellular logic (SPARCL) processors: system implementation,” submitted to J. Lightwave Technol.

Chirovsky, L. M. F.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, “1-Gb/s two-beam transimpedance smart pixel optical receivers made from hybrid GaAs MQW modulators bonded to 0.8 µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Choudhary, A. K.

J. M. del Rosario, A. K. Choudhary, “High-performance I/O for massively parallel computers—problems and prospects,” IEEE Comput. 27(3), 59–68 (1994).
[CrossRef]

Cunningham, J. E.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, “1-Gb/s two-beam transimpedance smart pixel optical receivers made from hybrid GaAs MQW modulators bonded to 0.8 µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

D’Asaro, L. A.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, “1-Gb/s two-beam transimpedance smart pixel optical receivers made from hybrid GaAs MQW modulators bonded to 0.8 µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D’Asaro, S. P. Hui, B. Tseng, “3-D integration of MQW modulators over active sub-micron CMOS circuits: 375Mb/s transimpedance receiver–transmitter circuit,” IEEE Photon. Technol. Lett. 7, 1288–1290 (1995).
[CrossRef]

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Dahringer, D.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

del Rosario, J. M.

J. M. del Rosario, A. K. Choudhary, “High-performance I/O for massively parallel computers—problems and prospects,” IEEE Comput. 27(3), 59–68 (1994).
[CrossRef]

Fernandes, J. M.

H. D. Santos, J. C. Ramalho, J. M. Fernandes, A. J. Proenca, “A heterogeneous computer vision architecture: implementation issues,” Comput. Syst. Eng. 6, 401–408 (1995).
[CrossRef]

Ford, J. E.

A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D’Asaro, S. P. Hui, B. Tseng, “3-D integration of MQW modulators over active sub-micron CMOS circuits: 375Mb/s transimpedance receiver–transmitter circuit,” IEEE Photon. Technol. Lett. 7, 1288–1290 (1995).
[CrossRef]

A. V. Krishnamoorthy, R. G. Rozier, J. E. Ford, F. E. Kiamilev, “Demonstration of a CMOS static RAM chip with high-speed optical read and write,” in Spatial Light Modulators, G. Burdge, S. Esener, eds., Vol. 14 of OSA Trends in Optics and Photonics Series (Optical Society of America, Washington, D.C., 1997), pp. 23–26.

Fujita, Y.

S. Okazaki, Y. Fujita, N. Yamashita, “A compact real-time vision system using integrated memory array processor architecture,” IEEE Trans. Circ. Syst. Video Technol. 5, 446–452 (1995).
[CrossRef]

Glaser, I.

Goodenough, J.

J. Goodenough, R. J. Meacham, J. D. Morris, N. L. Seed, P. A. Ivey, “A single chip video signal processing architecture for image processing, coding, and computer vision,” IEEE Trans. Circ. Syst. Video Technol. 5, 436–445 (1995).
[CrossRef]

Goossen, K. W.

A. V. Krishnamoorthy, K. W. Goossen, “Progress in optoelectronic-VLSI smart pixel technology based on GaAs/AlGaAs MQW modulators,” Int. J. Optoelectron. 11, 181–198 (1997).

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, “1-Gb/s two-beam transimpedance smart pixel optical receivers made from hybrid GaAs MQW modulators bonded to 0.8 µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D’Asaro, S. P. Hui, B. Tseng, “3-D integration of MQW modulators over active sub-micron CMOS circuits: 375Mb/s transimpedance receiver–transmitter circuit,” IEEE Photon. Technol. Lett. 7, 1288–1290 (1995).
[CrossRef]

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Gregoretti, F.

A. Broggi, F. Gregoretti, “Performance evaluation and optimization in low-cost cellular SIMD systems,” Microprocess. Microprogramm. 41, 659–678 (1996).
[CrossRef]

Hoanca, B.

C. B. Kuznia, J.-M. Wu, C.-H. Chen, B. Hoanca, L. Cheng, A. G. Weber, A. A. Sawchuk, “Two-dimensional parallel pipeline processing with smart pixel array cellular logic (SPARCL) processors: system implementation,” submitted to J. Lightwave Technol.

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, A. A. Sawchuk, “Integration of CMOS/MQW smart pixel array cellular logic (SPARCL) processors for SIMD parallel pipeline processing,” presented at the 1997 North American Chinese Photonics Technology Conference, Los Angeles, Calif., 17–19 October 1997.

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, L. Cheng, A. G. Weber, A. A. Sawchuk, “Smart pixel array cellular logic (SPARCL) processor for eliminating SIMD I/O bottlenecks: system demonstration and performance scaling,” in Optics in Computing, Vol. 8 of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 152–154.

Huang, K.-S.

Hui, S. P.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D’Asaro, S. P. Hui, B. Tseng, “3-D integration of MQW modulators over active sub-micron CMOS circuits: 375Mb/s transimpedance receiver–transmitter circuit,” IEEE Photon. Technol. Lett. 7, 1288–1290 (1995).
[CrossRef]

Hwang, K.

K. Hwang, Advanced Computer Architecture: Parallelism, Scalability, Programmability (McGraw-Hill, New York, 1994).

Ivey, P. A.

J. Goodenough, R. J. Meacham, J. D. Morris, N. L. Seed, P. A. Ivey, “A single chip video signal processing architecture for image processing, coding, and computer vision,” IEEE Trans. Circ. Syst. Video Technol. 5, 436–445 (1995).
[CrossRef]

Jan, W. Y.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, “1-Gb/s two-beam transimpedance smart pixel optical receivers made from hybrid GaAs MQW modulators bonded to 0.8 µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

Jenkins, B. K.

Kiamilev, F. E.

A. V. Krishnamoorthy, R. G. Rozier, J. E. Ford, F. E. Kiamilev, “Demonstration of a CMOS static RAM chip with high-speed optical read and write,” in Spatial Light Modulators, G. Burdge, S. Esener, eds., Vol. 14 of OSA Trends in Optics and Photonics Series (Optical Society of America, Washington, D.C., 1997), pp. 23–26.

F. E. Kiamilev, R. G. Rozier, “Design of optoelectronic-VLSI ICs for optically accessed SRAMs,” in Spatial Light Modulators, G. Burdge, S. Esener, eds., Vol. 14 of OSA Trends in Optics and Photonics Series (Optical Society of America, Washington, D.C., 1997), pp. 11–13.

Kossives, D.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Krishnamoorthy, A. V.

A. V. Krishnamoorthy, K. W. Goossen, “Progress in optoelectronic-VLSI smart pixel technology based on GaAs/AlGaAs MQW modulators,” Int. J. Optoelectron. 11, 181–198 (1997).

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, “1-Gb/s two-beam transimpedance smart pixel optical receivers made from hybrid GaAs MQW modulators bonded to 0.8 µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D’Asaro, S. P. Hui, B. Tseng, “3-D integration of MQW modulators over active sub-micron CMOS circuits: 375Mb/s transimpedance receiver–transmitter circuit,” IEEE Photon. Technol. Lett. 7, 1288–1290 (1995).
[CrossRef]

A. V. Krishnamoorthy, R. G. Rozier, J. E. Ford, F. E. Kiamilev, “Demonstration of a CMOS static RAM chip with high-speed optical read and write,” in Spatial Light Modulators, G. Burdge, S. Esener, eds., Vol. 14 of OSA Trends in Optics and Photonics Series (Optical Society of America, Washington, D.C., 1997), pp. 23–26.

Kuznia, C. B.

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, A. A. Sawchuk, “Integration of CMOS/MQW smart pixel array cellular logic (SPARCL) processors for SIMD parallel pipeline processing,” presented at the 1997 North American Chinese Photonics Technology Conference, Los Angeles, Calif., 17–19 October 1997.

C. B. Kuznia, J.-M. Wu, C.-H. Chen, A. A. Sawchuk, L. Cheng, “Hybrid CMOS/SEED smart pixel array for 2D parallel pipeline operations,” in Digest IEEE/LEOS 1996 Summer Topical Meetings: Smart Pixels (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1996), pp. 80–81.
[CrossRef]

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, L. Cheng, A. G. Weber, A. A. Sawchuk, “Smart pixel array cellular logic (SPARCL) processor for eliminating SIMD I/O bottlenecks: system demonstration and performance scaling,” in Optics in Computing, Vol. 8 of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 152–154.

C. B. Kuznia, J.-M. Wu, C.-H. Chen, B. Hoanca, L. Cheng, A. G. Weber, A. A. Sawchuk, “Two-dimensional parallel pipeline processing with smart pixel array cellular logic (SPARCL) processors: system implementation,” submitted to J. Lightwave Technol.

Le Gall, D.

D. Le Gall, “MPEG: a video compression standard for multimedia applications,” Commun. ACM 34, 46–58 (1991).
[CrossRef]

Leibenguth, R.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Lentine, A. L.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, “1-Gb/s two-beam transimpedance smart pixel optical receivers made from hybrid GaAs MQW modulators bonded to 0.8 µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D’Asaro, S. P. Hui, B. Tseng, “3-D integration of MQW modulators over active sub-micron CMOS circuits: 375Mb/s transimpedance receiver–transmitter circuit,” IEEE Photon. Technol. Lett. 7, 1288–1290 (1995).
[CrossRef]

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Maragos, P.

P. Maragos, R. Shafer, “Morphological systems for multidimensional signal processing,” Proc. IEEE 78, 690–709 (1990).
[CrossRef]

Meacham, R. J.

J. Goodenough, R. J. Meacham, J. D. Morris, N. L. Seed, P. A. Ivey, “A single chip video signal processing architecture for image processing, coding, and computer vision,” IEEE Trans. Circ. Syst. Video Technol. 5, 436–445 (1995).
[CrossRef]

Miller, D. A. B.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Morris, J. D.

J. Goodenough, R. J. Meacham, J. D. Morris, N. L. Seed, P. A. Ivey, “A single chip video signal processing architecture for image processing, coding, and computer vision,” IEEE Trans. Circ. Syst. Video Technol. 5, 436–445 (1995).
[CrossRef]

Okazaki, S.

S. Okazaki, Y. Fujita, N. Yamashita, “A compact real-time vision system using integrated memory array processor architecture,” IEEE Trans. Circ. Syst. Video Technol. 5, 446–452 (1995).
[CrossRef]

Proenca, A. J.

H. D. Santos, J. C. Ramalho, J. M. Fernandes, A. J. Proenca, “A heterogeneous computer vision architecture: implementation issues,” Comput. Syst. Eng. 6, 401–408 (1995).
[CrossRef]

Ramalho, J. C.

H. D. Santos, J. C. Ramalho, J. M. Fernandes, A. J. Proenca, “A heterogeneous computer vision architecture: implementation issues,” Comput. Syst. Eng. 6, 401–408 (1995).
[CrossRef]

Rozier, R. G.

A. V. Krishnamoorthy, R. G. Rozier, J. E. Ford, F. E. Kiamilev, “Demonstration of a CMOS static RAM chip with high-speed optical read and write,” in Spatial Light Modulators, G. Burdge, S. Esener, eds., Vol. 14 of OSA Trends in Optics and Photonics Series (Optical Society of America, Washington, D.C., 1997), pp. 23–26.

F. E. Kiamilev, R. G. Rozier, “Design of optoelectronic-VLSI ICs for optically accessed SRAMs,” in Spatial Light Modulators, G. Burdge, S. Esener, eds., Vol. 14 of OSA Trends in Optics and Photonics Series (Optical Society of America, Washington, D.C., 1997), pp. 11–13.

Santos, H. D.

H. D. Santos, J. C. Ramalho, J. M. Fernandes, A. J. Proenca, “A heterogeneous computer vision architecture: implementation issues,” Comput. Syst. Eng. 6, 401–408 (1995).
[CrossRef]

Sawchuk, A. A.

K.-S. Huang, A. A. Sawchuk, B. K. Jenkins, P. Chavel, J.-M. Wang, A. G. Weber, C.-H. Wang, I. Glaser, “Digital optical cellular image processor (DOCIP): experimental implementation,” Appl. Opt. 32, 166–173 (1993).
[CrossRef] [PubMed]

K.-S. Huang, B. K. Jenkins, A. A. Sawchuk, “Image algebra representation of parallel optical binary arithmetic,” Appl. Opt. 28, 1263–1278 (1989).
[CrossRef] [PubMed]

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, A. A. Sawchuk, “Integration of CMOS/MQW smart pixel array cellular logic (SPARCL) processors for SIMD parallel pipeline processing,” presented at the 1997 North American Chinese Photonics Technology Conference, Los Angeles, Calif., 17–19 October 1997.

A. A. Sawchuk, “Optoelectronic memory applications for VCSEL-based smart pixels,” in Proceedings, IEEE Lasers and Electro-Optics Society 1997 Annual Meeting (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1997), pp. 149–150.

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, L. Cheng, A. G. Weber, A. A. Sawchuk, “Smart pixel array cellular logic (SPARCL) processor for eliminating SIMD I/O bottlenecks: system demonstration and performance scaling,” in Optics in Computing, Vol. 8 of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 152–154.

C. B. Kuznia, J.-M. Wu, C.-H. Chen, B. Hoanca, L. Cheng, A. G. Weber, A. A. Sawchuk, “Two-dimensional parallel pipeline processing with smart pixel array cellular logic (SPARCL) processors: system implementation,” submitted to J. Lightwave Technol.

A. A. Sawchuk, “Smart pixel devices and free-space digital optics applications,” in Proceedings of 1995 IEEE/LEOS Annual Meeting (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1995), pp. 268–269.

C. B. Kuznia, J.-M. Wu, C.-H. Chen, A. A. Sawchuk, L. Cheng, “Hybrid CMOS/SEED smart pixel array for 2D parallel pipeline operations,” in Digest IEEE/LEOS 1996 Summer Topical Meetings: Smart Pixels (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1996), pp. 80–81.
[CrossRef]

Schimmel, D. E.

J. D. Allen, D. E. Schimmel, “Issues in the design of high performance SIMD architectures,” IEEE Trans. Parallel Distr. Syst. 7, 818–829 (1996).
[CrossRef]

Seed, N. L.

J. Goodenough, R. J. Meacham, J. D. Morris, N. L. Seed, P. A. Ivey, “A single chip video signal processing architecture for image processing, coding, and computer vision,” IEEE Trans. Circ. Syst. Video Technol. 5, 436–445 (1995).
[CrossRef]

Shafer, R.

P. Maragos, R. Shafer, “Morphological systems for multidimensional signal processing,” Proc. IEEE 78, 690–709 (1990).
[CrossRef]

Tseng, B.

A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D’Asaro, S. P. Hui, B. Tseng, “3-D integration of MQW modulators over active sub-micron CMOS circuits: 375Mb/s transimpedance receiver–transmitter circuit,” IEEE Photon. Technol. Lett. 7, 1288–1290 (1995).
[CrossRef]

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Walker, J. A.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, “1-Gb/s two-beam transimpedance smart pixel optical receivers made from hybrid GaAs MQW modulators bonded to 0.8 µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D’Asaro, S. P. Hui, B. Tseng, “3-D integration of MQW modulators over active sub-micron CMOS circuits: 375Mb/s transimpedance receiver–transmitter circuit,” IEEE Photon. Technol. Lett. 7, 1288–1290 (1995).
[CrossRef]

Wang, C.-H.

Wang, J.-M.

Weber, A. G.

K.-S. Huang, A. A. Sawchuk, B. K. Jenkins, P. Chavel, J.-M. Wang, A. G. Weber, C.-H. Wang, I. Glaser, “Digital optical cellular image processor (DOCIP): experimental implementation,” Appl. Opt. 32, 166–173 (1993).
[CrossRef] [PubMed]

C. B. Kuznia, J.-M. Wu, C.-H. Chen, B. Hoanca, L. Cheng, A. G. Weber, A. A. Sawchuk, “Two-dimensional parallel pipeline processing with smart pixel array cellular logic (SPARCL) processors: system implementation,” submitted to J. Lightwave Technol.

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, L. Cheng, A. G. Weber, A. A. Sawchuk, “Smart pixel array cellular logic (SPARCL) processor for eliminating SIMD I/O bottlenecks: system demonstration and performance scaling,” in Optics in Computing, Vol. 8 of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 152–154.

Woodward, T. K.

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, “1-Gb/s two-beam transimpedance smart pixel optical receivers made from hybrid GaAs MQW modulators bonded to 0.8 µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D’Asaro, S. P. Hui, B. Tseng, “3-D integration of MQW modulators over active sub-micron CMOS circuits: 375Mb/s transimpedance receiver–transmitter circuit,” IEEE Photon. Technol. Lett. 7, 1288–1290 (1995).
[CrossRef]

Wu, J.-M.

C. B. Kuznia, J.-M. Wu, C.-H. Chen, A. A. Sawchuk, L. Cheng, “Hybrid CMOS/SEED smart pixel array for 2D parallel pipeline operations,” in Digest IEEE/LEOS 1996 Summer Topical Meetings: Smart Pixels (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1996), pp. 80–81.
[CrossRef]

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, L. Cheng, A. G. Weber, A. A. Sawchuk, “Smart pixel array cellular logic (SPARCL) processor for eliminating SIMD I/O bottlenecks: system demonstration and performance scaling,” in Optics in Computing, Vol. 8 of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 152–154.

C. B. Kuznia, J.-M. Wu, C.-H. Chen, B. Hoanca, L. Cheng, A. G. Weber, A. A. Sawchuk, “Two-dimensional parallel pipeline processing with smart pixel array cellular logic (SPARCL) processors: system implementation,” submitted to J. Lightwave Technol.

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, A. A. Sawchuk, “Integration of CMOS/MQW smart pixel array cellular logic (SPARCL) processors for SIMD parallel pipeline processing,” presented at the 1997 North American Chinese Photonics Technology Conference, Los Angeles, Calif., 17–19 October 1997.

Yamashita, N.

S. Okazaki, Y. Fujita, N. Yamashita, “A compact real-time vision system using integrated memory array processor architecture,” IEEE Trans. Circ. Syst. Video Technol. 5, 446–452 (1995).
[CrossRef]

Appl. Opt. (2)

Commun. ACM (1)

D. Le Gall, “MPEG: a video compression standard for multimedia applications,” Commun. ACM 34, 46–58 (1991).
[CrossRef]

Comput. Syst. Eng. (1)

H. D. Santos, J. C. Ramalho, J. M. Fernandes, A. J. Proenca, “A heterogeneous computer vision architecture: implementation issues,” Comput. Syst. Eng. 6, 401–408 (1995).
[CrossRef]

IEEE Comput. (1)

J. M. del Rosario, A. K. Choudhary, “High-performance I/O for massively parallel computers—problems and prospects,” IEEE Comput. 27(3), 59–68 (1994).
[CrossRef]

IEEE Photon. Technol. Lett. (3)

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photon. Technol. Lett. 7, 360–362 (1995).
[CrossRef]

A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, T. K. Woodward, J. E. Ford, G. F. Aplin, L. A. D’Asaro, S. P. Hui, B. Tseng, “3-D integration of MQW modulators over active sub-micron CMOS circuits: 375Mb/s transimpedance receiver–transmitter circuit,” IEEE Photon. Technol. Lett. 7, 1288–1290 (1995).
[CrossRef]

T. K. Woodward, A. V. Krishnamoorthy, A. L. Lentine, K. W. Goossen, J. A. Walker, J. E. Cunningham, W. Y. Jan, L. A. D’Asaro, L. M. F. Chirovsky, “1-Gb/s two-beam transimpedance smart pixel optical receivers made from hybrid GaAs MQW modulators bonded to 0.8 µm silicon CMOS,” IEEE Photon. Technol. Lett. 8, 422–424 (1996).
[CrossRef]

IEEE Trans. Circ. Syst. Video Technol. (2)

J. Goodenough, R. J. Meacham, J. D. Morris, N. L. Seed, P. A. Ivey, “A single chip video signal processing architecture for image processing, coding, and computer vision,” IEEE Trans. Circ. Syst. Video Technol. 5, 436–445 (1995).
[CrossRef]

S. Okazaki, Y. Fujita, N. Yamashita, “A compact real-time vision system using integrated memory array processor architecture,” IEEE Trans. Circ. Syst. Video Technol. 5, 446–452 (1995).
[CrossRef]

IEEE Trans. Parallel Distr. Syst. (1)

J. D. Allen, D. E. Schimmel, “Issues in the design of high performance SIMD architectures,” IEEE Trans. Parallel Distr. Syst. 7, 818–829 (1996).
[CrossRef]

Int. J. Optoelectron. (1)

A. V. Krishnamoorthy, K. W. Goossen, “Progress in optoelectronic-VLSI smart pixel technology based on GaAs/AlGaAs MQW modulators,” Int. J. Optoelectron. 11, 181–198 (1997).

Microprocess. Microprogramm. (1)

A. Broggi, F. Gregoretti, “Performance evaluation and optimization in low-cost cellular SIMD systems,” Microprocess. Microprogramm. 41, 659–678 (1996).
[CrossRef]

Proc. IEEE (1)

P. Maragos, R. Shafer, “Morphological systems for multidimensional signal processing,” Proc. IEEE 78, 690–709 (1990).
[CrossRef]

Other (10)

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, L. Cheng, A. G. Weber, A. A. Sawchuk, “Smart pixel array cellular logic (SPARCL) processor for eliminating SIMD I/O bottlenecks: system demonstration and performance scaling,” in Optics in Computing, Vol. 8 of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 152–154.

J.-M. Wu, C. B. Kuznia, B. Hoanca, C.-H. Chen, A. A. Sawchuk, “Integration of CMOS/MQW smart pixel array cellular logic (SPARCL) processors for SIMD parallel pipeline processing,” presented at the 1997 North American Chinese Photonics Technology Conference, Los Angeles, Calif., 17–19 October 1997.

A. A. Sawchuk, “Optoelectronic memory applications for VCSEL-based smart pixels,” in Proceedings, IEEE Lasers and Electro-Optics Society 1997 Annual Meeting (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1997), pp. 149–150.

A. V. Krishnamoorthy, R. G. Rozier, J. E. Ford, F. E. Kiamilev, “Demonstration of a CMOS static RAM chip with high-speed optical read and write,” in Spatial Light Modulators, G. Burdge, S. Esener, eds., Vol. 14 of OSA Trends in Optics and Photonics Series (Optical Society of America, Washington, D.C., 1997), pp. 23–26.

F. E. Kiamilev, R. G. Rozier, “Design of optoelectronic-VLSI ICs for optically accessed SRAMs,” in Spatial Light Modulators, G. Burdge, S. Esener, eds., Vol. 14 of OSA Trends in Optics and Photonics Series (Optical Society of America, Washington, D.C., 1997), pp. 11–13.

K. Hwang, Advanced Computer Architecture: Parallelism, Scalability, Programmability (McGraw-Hill, New York, 1994).

A. A. Sawchuk, “Smart pixel devices and free-space digital optics applications,” in Proceedings of 1995 IEEE/LEOS Annual Meeting (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1995), pp. 268–269.

Semiconductor Industry Association, The National Technology Roadmap for Semiconductors (Sematech, Inc., San Jose, Calif., 1997).

C. B. Kuznia, J.-M. Wu, C.-H. Chen, A. A. Sawchuk, L. Cheng, “Hybrid CMOS/SEED smart pixel array for 2D parallel pipeline operations,” in Digest IEEE/LEOS 1996 Summer Topical Meetings: Smart Pixels (Institute of Electrical and Electronics Engineers, Piscataway, N.J., 1996), pp. 80–81.
[CrossRef]

C. B. Kuznia, J.-M. Wu, C.-H. Chen, B. Hoanca, L. Cheng, A. G. Weber, A. A. Sawchuk, “Two-dimensional parallel pipeline processing with smart pixel array cellular logic (SPARCL) processors: system implementation,” submitted to J. Lightwave Technol.

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Figures (11)

Fig. 1
Fig. 1

SPARCL system prototype.

Fig. 2
Fig. 2

Architectural comparison of (a) a conventional SIMD machine, (b) a 1D nSPARCL with electrically loaded input and output, and (c) a 2D nSPARCL with optically loaded input and output. All systems are assumed have the same number of total processing elements.

Fig. 3
Fig. 3

Block diagram of a BIA smart-pixel design: Q and Q¯, a memory output and its complement, respectively.

Fig. 4
Fig. 4

Optical I/O of a smart pixel.

Fig. 5
Fig. 5

Physical layout of the 5 × 10 SPARCL chip.

Fig. 6
Fig. 6

Demonstration of the SPARCL system for image edge detection.

Fig. 7
Fig. 7

SPARCL for motion estimation. (a) Encoding and transmission, (b) receiving and frame recovery. At transmitter site, two consecutive video frames (at the left) and the difference image and motion vectors (at the right) are computed by the SPARCL system. Player number 18 moves upward in the image frames, leaving his imprint in the difference image. The current frame can be recovered easily at the receiver site.

Fig. 8
Fig. 8

Timing chart of data block processing for a SIMD system, a four-stage 1D nSPARCL, and a four stage 2D nSPARCL.

Fig. 9
Fig. 9

Comparison of ratio of total processing times of n = 3, 4, 9, 25nSPARCL’s and equivalent SIMD systems plotted against the time needed for processing operations, T exe.

Fig. 10
Fig. 10

Comparison of bus utilization of n = 3, 4, 9, 25nSPARCL’s and equivalent SIMD systems.

Fig. 11
Fig. 11

Comparison of processing speed (in terms of pixels/clock cycle) with the number of processing elements for SIMD, 1D nSPARCL, and 2D nSPARCL systems. The 2D nSPARCL eliminates the data I/O bottleneck by performing 2D parallel data I/O with input and output devices.

Tables (1)

Tables Icon

Table 1 Prototype Chip Parameters

Equations (11)

Equations on this page are rendered with MathJax. Learn more.

X¯=x, y|x, y  W, x, yX=W-X;
XY=x, y|x, yX orx, yY,
XR=p, q|Rp,qXØ,
010111010
Z=X¯X¯R¯,
D=B0¯B1¯
Spr=N2Tload+Texe+Tunload,
TSIMD=N2npqnq+Texe,
T1-D_nSPARCL = N2pqq+1Texen-2q,N2pqTexe+2q+nnTexen-2>q.
nopt=TexeTload+2,
T2-D_nSPARCL=N2pq1+Texen.

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