Abstract

A concept for a parallel digital signal processor based on optical interconnections and optoelectronic VLSI circuits is presented. It is shown that the proper combination of optical communication, architecture, and algorithms allows a throughput that outperforms purely electronic solutions. The usefulness of low-level algorithms from the add-and-shift class is emphasized. These algorithms lead to fine-grain, massively parallel on-chip processor architectures with high demands for optical off-chip interconnections. A comparative performance analysis shows the superiority of a bit-serial architecture. This architecture is mapped onto an optoelectronic three-dimensional circuit, and the necessary optical interconnection scheme is specified.

© 1998 Optical Society of America

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  1. G. Sai-Halasz, “Performance trends in high-end processors,” Proc. IEEE 83, 20–36 (1995).
    [CrossRef]
  2. K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
    [CrossRef]
  3. A. V. Krishnamoorthy, D. A. B. Miller, “Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Sel. Top. Quantum Electron. 2, 55–75 (1996).
    [CrossRef]
  4. T. K. Woodward, “VSLI-compatible smart-pixel circuits and technology,” in Smart Pixel Digital Digest (Institute of Electrical and Electronics Engineers, New York, 1996), p. 65.
  5. S. Araki, M. Kajita, K. Kubota, K. Kurihara, I. Redmond, E. Schenfeld, T. Suzaki, “Experimental free-space optical network for massively parallel computers,” Appl. Opt. 35, 1269–1281 (1996).
    [CrossRef] [PubMed]
  6. J. Jahns, “Planar packaging of free space optical interconnections,” Proc. IEEE 82, 1623–1631 (1994).
    [CrossRef]
  7. F. B. McCormick, F. A. P. Tooley, T. J. Cloonan, J. L. Brubaker, A. L. Lentine, R. L. Morrison, S. J. Hinterlong, M. J. Herron, S. L. Walker, J. M. Sasian, “Experimental investigation of free-space optical switching network by using symmetric self-electro-optic-effect devices,” Appl. Opt. 31, 5431–5446 (1992).
    [CrossRef] [PubMed]
  8. J. A. Neff, C. Chen, T. McLaren, C.-C. Mao, A. Fedor, W. Berseth, Y. C. Lee, V. Morozov, “VCSEL/CMOS smart pixel arrays for free-space optical interconnects,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 282–289.
  9. The mention of brand names in this paper is for information purposes only and does not constitute an endorsement of the product by the authors or their institutions (Synopsys Corp.).
  10. A. V. Krishnamoorthy, P. J. Marchand, F. E. Kiamilev, S. C. Esener, “Grain-size considerations for optoelectronic multistage interconnection networks,” Appl. Opt. 31, 5480–5507 (1992).
    [CrossRef] [PubMed]
  11. D. Fey, W. Erhard, “Algorithms for high-performance computing with smart pixels,” in Applications of Photonic Technology, G. A. Lampropoulos, J. Chrostowski, R. M. Measures, eds. (Plenum, New York, 1995), pp. 97–100.
  12. D. Fey, A. Kurschat, B. Kasche, W. Erhard, “A 3D optoelectronic processor for smart pixel processing units,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 344–351.
  13. M. Ishikawa, “System architecture for integrated optoelectronic computing,” Optoelectron. Devices Technol. 9, 29–36 (1994).
  14. J. Volder, “The CORDIC trigonometric computing technique,” IRE Trans. Electron. Comput. EC-8, 330–334 (1959).
    [CrossRef]
  15. B. Kasche, D. Fey, “Optimale Algorithmen zur Berechnung von Standardfunktionen mittels Smart Pixel Rechenwerke,” Tech. Rep., in Berichte zur Rechnerarchitektur, W. Erhard, ed. (University of Jena, Jena, Germany, 1996), Vol. 2.
  16. I. Koren, Computer Arithmetic Algorithms (Prentice-Hall, Englewood Cliffs, N.J., 1993).
  17. K. Hwang, Computer Arithmetic—Principles, Architecture and Design (Wiley, New York, 1979).
  18. A. R. Omondi, Computer Arithmetic Systems: Algorithms, Architecture and Implementation (Prentice-Hall, Englewood Cliffs, N.J., 1994).
  19. J. Slansky, “An evaluation of several two-summand binary adders,” IRE Trans. EC-9, 213–226 (1960).
  20. G. Grimm, “Entwicklung eines VLSI Layouts für optoelektronische programmierbare Schaltkreise,” Tech. Rep., in Berichte zur Rechnerarchitektur, W. Erhard, ed. (University of Jena, Jena, Germany, 1997), Vol. 3.
  21. U. Krackhardt, N. Streibl, “Design of Dammann-gratings for array generation,” Opt. Commun. 74, 31–36 (1989).
    [CrossRef]
  22. A. W. Lohmann, J. A. Thomas, “Making an array illuminator based on the Talbot effect,” Appl. Opt. 29, 4337–4340 (1990).
    [CrossRef] [PubMed]
  23. V. Sieh, O. Tschäche, F. Balbach, “Evalutaion of dependable systems using verify,” in Preprint of the Sixth Conference on Dependable Computing for Critical Applications (DCCA-6), M. Dal Cin, ed. (Grainau, Germany, 1997), pp. 59–76.
  24. V. Sieh, O. Tschäche, F. Balbach. verify: evaluation of reliability using VHDL-models with embedded fault descriptions, in Proceedings of the Twenty-Seventh Annual International Symposium on Fault-Tolerant Computing (FTCS-27), P. Storms, ed. (Institute of Electrical and Electronics Engineers, New York, 1997), pp. 32–36.

1996

A. V. Krishnamoorthy, D. A. B. Miller, “Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Sel. Top. Quantum Electron. 2, 55–75 (1996).
[CrossRef]

S. Araki, M. Kajita, K. Kubota, K. Kurihara, I. Redmond, E. Schenfeld, T. Suzaki, “Experimental free-space optical network for massively parallel computers,” Appl. Opt. 35, 1269–1281 (1996).
[CrossRef] [PubMed]

1995

G. Sai-Halasz, “Performance trends in high-end processors,” Proc. IEEE 83, 20–36 (1995).
[CrossRef]

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

1994

M. Ishikawa, “System architecture for integrated optoelectronic computing,” Optoelectron. Devices Technol. 9, 29–36 (1994).

J. Jahns, “Planar packaging of free space optical interconnections,” Proc. IEEE 82, 1623–1631 (1994).
[CrossRef]

1992

1990

1989

U. Krackhardt, N. Streibl, “Design of Dammann-gratings for array generation,” Opt. Commun. 74, 31–36 (1989).
[CrossRef]

1960

J. Slansky, “An evaluation of several two-summand binary adders,” IRE Trans. EC-9, 213–226 (1960).

1959

J. Volder, “The CORDIC trigonometric computing technique,” IRE Trans. Electron. Comput. EC-8, 330–334 (1959).
[CrossRef]

Araki, S.

Bacon, D. D.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Balbach, F.

V. Sieh, O. Tschäche, F. Balbach, “Evalutaion of dependable systems using verify,” in Preprint of the Sixth Conference on Dependable Computing for Critical Applications (DCCA-6), M. Dal Cin, ed. (Grainau, Germany, 1997), pp. 59–76.

V. Sieh, O. Tschäche, F. Balbach. verify: evaluation of reliability using VHDL-models with embedded fault descriptions, in Proceedings of the Twenty-Seventh Annual International Symposium on Fault-Tolerant Computing (FTCS-27), P. Storms, ed. (Institute of Electrical and Electronics Engineers, New York, 1997), pp. 32–36.

Berseth, W.

J. A. Neff, C. Chen, T. McLaren, C.-C. Mao, A. Fedor, W. Berseth, Y. C. Lee, V. Morozov, “VCSEL/CMOS smart pixel arrays for free-space optical interconnects,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 282–289.

Brubaker, J. L.

Chen, C.

J. A. Neff, C. Chen, T. McLaren, C.-C. Mao, A. Fedor, W. Berseth, Y. C. Lee, V. Morozov, “VCSEL/CMOS smart pixel arrays for free-space optical interconnects,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 282–289.

Chirovsky, L. M. F.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Cloonan, T. J.

D’Asaro, L. A.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Dahringer, D.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Erhard, W.

D. Fey, W. Erhard, “Algorithms for high-performance computing with smart pixels,” in Applications of Photonic Technology, G. A. Lampropoulos, J. Chrostowski, R. M. Measures, eds. (Plenum, New York, 1995), pp. 97–100.

D. Fey, A. Kurschat, B. Kasche, W. Erhard, “A 3D optoelectronic processor for smart pixel processing units,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 344–351.

Esener, S. C.

Fedor, A.

J. A. Neff, C. Chen, T. McLaren, C.-C. Mao, A. Fedor, W. Berseth, Y. C. Lee, V. Morozov, “VCSEL/CMOS smart pixel arrays for free-space optical interconnects,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 282–289.

Fey, D.

D. Fey, W. Erhard, “Algorithms for high-performance computing with smart pixels,” in Applications of Photonic Technology, G. A. Lampropoulos, J. Chrostowski, R. M. Measures, eds. (Plenum, New York, 1995), pp. 97–100.

D. Fey, A. Kurschat, B. Kasche, W. Erhard, “A 3D optoelectronic processor for smart pixel processing units,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 344–351.

B. Kasche, D. Fey, “Optimale Algorithmen zur Berechnung von Standardfunktionen mittels Smart Pixel Rechenwerke,” Tech. Rep., in Berichte zur Rechnerarchitektur, W. Erhard, ed. (University of Jena, Jena, Germany, 1996), Vol. 2.

Goossen, K. W.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Grimm, G.

G. Grimm, “Entwicklung eines VLSI Layouts für optoelektronische programmierbare Schaltkreise,” Tech. Rep., in Berichte zur Rechnerarchitektur, W. Erhard, ed. (University of Jena, Jena, Germany, 1997), Vol. 3.

Herron, M. J.

Hinterlong, S. J.

Hui, S. P.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Hwang, K.

K. Hwang, Computer Arithmetic—Principles, Architecture and Design (Wiley, New York, 1979).

Ishikawa, M.

M. Ishikawa, “System architecture for integrated optoelectronic computing,” Optoelectron. Devices Technol. 9, 29–36 (1994).

Jahns, J.

J. Jahns, “Planar packaging of free space optical interconnections,” Proc. IEEE 82, 1623–1631 (1994).
[CrossRef]

Kajita, M.

Kasche, B.

D. Fey, A. Kurschat, B. Kasche, W. Erhard, “A 3D optoelectronic processor for smart pixel processing units,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 344–351.

B. Kasche, D. Fey, “Optimale Algorithmen zur Berechnung von Standardfunktionen mittels Smart Pixel Rechenwerke,” Tech. Rep., in Berichte zur Rechnerarchitektur, W. Erhard, ed. (University of Jena, Jena, Germany, 1996), Vol. 2.

Kiamilev, F. E.

Koren, I.

I. Koren, Computer Arithmetic Algorithms (Prentice-Hall, Englewood Cliffs, N.J., 1993).

Kossives, D.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Krackhardt, U.

U. Krackhardt, N. Streibl, “Design of Dammann-gratings for array generation,” Opt. Commun. 74, 31–36 (1989).
[CrossRef]

Krishnamoorthy, A. V.

A. V. Krishnamoorthy, D. A. B. Miller, “Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Sel. Top. Quantum Electron. 2, 55–75 (1996).
[CrossRef]

A. V. Krishnamoorthy, P. J. Marchand, F. E. Kiamilev, S. C. Esener, “Grain-size considerations for optoelectronic multistage interconnection networks,” Appl. Opt. 31, 5480–5507 (1992).
[CrossRef] [PubMed]

Kubota, K.

Kurihara, K.

Kurschat, A.

D. Fey, A. Kurschat, B. Kasche, W. Erhard, “A 3D optoelectronic processor for smart pixel processing units,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 344–351.

Lee, Y. C.

J. A. Neff, C. Chen, T. McLaren, C.-C. Mao, A. Fedor, W. Berseth, Y. C. Lee, V. Morozov, “VCSEL/CMOS smart pixel arrays for free-space optical interconnects,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 282–289.

Leibenguth, R.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Lentine, A. L.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

F. B. McCormick, F. A. P. Tooley, T. J. Cloonan, J. L. Brubaker, A. L. Lentine, R. L. Morrison, S. J. Hinterlong, M. J. Herron, S. L. Walker, J. M. Sasian, “Experimental investigation of free-space optical switching network by using symmetric self-electro-optic-effect devices,” Appl. Opt. 31, 5431–5446 (1992).
[CrossRef] [PubMed]

Lohmann, A. W.

Mao, C.-C.

J. A. Neff, C. Chen, T. McLaren, C.-C. Mao, A. Fedor, W. Berseth, Y. C. Lee, V. Morozov, “VCSEL/CMOS smart pixel arrays for free-space optical interconnects,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 282–289.

Marchand, P. J.

McCormick, F. B.

McLaren, T.

J. A. Neff, C. Chen, T. McLaren, C.-C. Mao, A. Fedor, W. Berseth, Y. C. Lee, V. Morozov, “VCSEL/CMOS smart pixel arrays for free-space optical interconnects,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 282–289.

Miller, D. A. B.

A. V. Krishnamoorthy, D. A. B. Miller, “Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Sel. Top. Quantum Electron. 2, 55–75 (1996).
[CrossRef]

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Morozov, V.

J. A. Neff, C. Chen, T. McLaren, C.-C. Mao, A. Fedor, W. Berseth, Y. C. Lee, V. Morozov, “VCSEL/CMOS smart pixel arrays for free-space optical interconnects,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 282–289.

Morrison, R. L.

Neff, J. A.

J. A. Neff, C. Chen, T. McLaren, C.-C. Mao, A. Fedor, W. Berseth, Y. C. Lee, V. Morozov, “VCSEL/CMOS smart pixel arrays for free-space optical interconnects,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 282–289.

Omondi, A. R.

A. R. Omondi, Computer Arithmetic Systems: Algorithms, Architecture and Implementation (Prentice-Hall, Englewood Cliffs, N.J., 1994).

Redmond, I.

Sai-Halasz, G.

G. Sai-Halasz, “Performance trends in high-end processors,” Proc. IEEE 83, 20–36 (1995).
[CrossRef]

Sasian, J. M.

Schenfeld, E.

Sieh, V.

V. Sieh, O. Tschäche, F. Balbach. verify: evaluation of reliability using VHDL-models with embedded fault descriptions, in Proceedings of the Twenty-Seventh Annual International Symposium on Fault-Tolerant Computing (FTCS-27), P. Storms, ed. (Institute of Electrical and Electronics Engineers, New York, 1997), pp. 32–36.

V. Sieh, O. Tschäche, F. Balbach, “Evalutaion of dependable systems using verify,” in Preprint of the Sixth Conference on Dependable Computing for Critical Applications (DCCA-6), M. Dal Cin, ed. (Grainau, Germany, 1997), pp. 59–76.

Slansky, J.

J. Slansky, “An evaluation of several two-summand binary adders,” IRE Trans. EC-9, 213–226 (1960).

Streibl, N.

U. Krackhardt, N. Streibl, “Design of Dammann-gratings for array generation,” Opt. Commun. 74, 31–36 (1989).
[CrossRef]

Suzaki, T.

Thomas, J. A.

Tooley, F. A. P.

Tschäche, O.

V. Sieh, O. Tschäche, F. Balbach, “Evalutaion of dependable systems using verify,” in Preprint of the Sixth Conference on Dependable Computing for Critical Applications (DCCA-6), M. Dal Cin, ed. (Grainau, Germany, 1997), pp. 59–76.

V. Sieh, O. Tschäche, F. Balbach. verify: evaluation of reliability using VHDL-models with embedded fault descriptions, in Proceedings of the Twenty-Seventh Annual International Symposium on Fault-Tolerant Computing (FTCS-27), P. Storms, ed. (Institute of Electrical and Electronics Engineers, New York, 1997), pp. 32–36.

Tseng, B.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Volder, J.

J. Volder, “The CORDIC trigonometric computing technique,” IRE Trans. Electron. Comput. EC-8, 330–334 (1959).
[CrossRef]

Walker, J. A.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

Walker, S. L.

Woodward, T. K.

T. K. Woodward, “VSLI-compatible smart-pixel circuits and technology,” in Smart Pixel Digital Digest (Institute of Electrical and Electronics Engineers, New York, 1996), p. 65.

Appl. Opt.

IEEE J. Sel. Top. Quantum Electron.

A. V. Krishnamoorthy, D. A. B. Miller, “Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Sel. Top. Quantum Electron. 2, 55–75 (1996).
[CrossRef]

IEEE Photonics Technol. Lett.

K. W. Goossen, J. A. Walker, L. A. D’Asaro, S. P. Hui, B. Tseng, R. Leibenguth, D. Kossives, D. D. Bacon, D. Dahringer, L. M. F. Chirovsky, A. L. Lentine, D. A. B. Miller, “GaAs MQW modulators integrated with silicon CMOS,” IEEE Photonics Technol. Lett. 7, 360–362 (1995).
[CrossRef]

IRE Trans.

J. Slansky, “An evaluation of several two-summand binary adders,” IRE Trans. EC-9, 213–226 (1960).

IRE Trans. Electron. Comput.

J. Volder, “The CORDIC trigonometric computing technique,” IRE Trans. Electron. Comput. EC-8, 330–334 (1959).
[CrossRef]

Opt. Commun.

U. Krackhardt, N. Streibl, “Design of Dammann-gratings for array generation,” Opt. Commun. 74, 31–36 (1989).
[CrossRef]

Optoelectron. Devices Technol.

M. Ishikawa, “System architecture for integrated optoelectronic computing,” Optoelectron. Devices Technol. 9, 29–36 (1994).

Proc. IEEE

G. Sai-Halasz, “Performance trends in high-end processors,” Proc. IEEE 83, 20–36 (1995).
[CrossRef]

J. Jahns, “Planar packaging of free space optical interconnections,” Proc. IEEE 82, 1623–1631 (1994).
[CrossRef]

Other

J. A. Neff, C. Chen, T. McLaren, C.-C. Mao, A. Fedor, W. Berseth, Y. C. Lee, V. Morozov, “VCSEL/CMOS smart pixel arrays for free-space optical interconnects,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 282–289.

The mention of brand names in this paper is for information purposes only and does not constitute an endorsement of the product by the authors or their institutions (Synopsys Corp.).

T. K. Woodward, “VSLI-compatible smart-pixel circuits and technology,” in Smart Pixel Digital Digest (Institute of Electrical and Electronics Engineers, New York, 1996), p. 65.

B. Kasche, D. Fey, “Optimale Algorithmen zur Berechnung von Standardfunktionen mittels Smart Pixel Rechenwerke,” Tech. Rep., in Berichte zur Rechnerarchitektur, W. Erhard, ed. (University of Jena, Jena, Germany, 1996), Vol. 2.

I. Koren, Computer Arithmetic Algorithms (Prentice-Hall, Englewood Cliffs, N.J., 1993).

K. Hwang, Computer Arithmetic—Principles, Architecture and Design (Wiley, New York, 1979).

A. R. Omondi, Computer Arithmetic Systems: Algorithms, Architecture and Implementation (Prentice-Hall, Englewood Cliffs, N.J., 1994).

G. Grimm, “Entwicklung eines VLSI Layouts für optoelektronische programmierbare Schaltkreise,” Tech. Rep., in Berichte zur Rechnerarchitektur, W. Erhard, ed. (University of Jena, Jena, Germany, 1997), Vol. 3.

D. Fey, W. Erhard, “Algorithms for high-performance computing with smart pixels,” in Applications of Photonic Technology, G. A. Lampropoulos, J. Chrostowski, R. M. Measures, eds. (Plenum, New York, 1995), pp. 97–100.

D. Fey, A. Kurschat, B. Kasche, W. Erhard, “A 3D optoelectronic processor for smart pixel processing units,” in Proceedings of MPPOI’96, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 344–351.

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Figures (12)

Fig. 1
Fig. 1

Digit algorithm structure.

Fig. 2
Fig. 2

Processor array of the DSP system.

Fig. 3
Fig. 3

One PE with the communication structure of a RCA. FA, full adder.

Fig. 4
Fig. 4

Communication structure of an 8-bit CSA in a time–PE diagram. MUX’s, multiplexer operations; HA, half adder.

Fig. 5
Fig. 5

Bit-serial PE vectors for a DSP system arranged in a matrix.

Fig. 6
Fig. 6

Partitioning of a PE with the corresponding optical I/O’s.

Fig. 7
Fig. 7

Optical interconnection scheme for one row of PE’s.

Fig. 8
Fig. 8

Setup of a PE in the bs approach. FF, flip-flop.

Fig. 9
Fig. 9

Comparison of the throughputs for each pair of bp (ripple carry), bp (CSA), and bs approaches.

Fig. 10
Fig. 10

Comparison of the expected performance of the optoelectronic bs DSP system with purely electronic architectures. MOPS, megaoperations per second; RISC, reduced instruction-set computing; CISC, complex instruction-set computing.

Fig. 11
Fig. 11

Schematic of the optoelectronic bs DSP architecture.

Fig. 12
Fig. 12

Optical model of the cross talk of one light beam to several receivers.

Tables (2)

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Table 1 Developed Uniform Low-Level Algorithms for Standard Functions

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Table 2 Number of Steps for One Iteration and for the Whole Calculation for the Different Investigated Architectural Models

Equations (23)

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log i = 1 n   y i = i = 1 n log y i .
ϕ = k = 1 n   α k - δ k ,
1 = ϕ   k = 1 n   α k δ k .
y n   : =   ϕ   k = 1 n   α k δ k .
y n + 1 = y n + y n 2 - n + 1 .
ϕ = k = 1 n   α k - δ k + R ϕ ,   n .
log ϕ = log k = 1 n   α k - δ k + R ϕ ,   n .
log ϕ = log k = 1 n α k - δ k = - k = 1 n log α k δ k .
x n + 1 : =   x n - log   α n δ n .
δ k   : =   0 1 if   y k + 1 > 1 else .
x 0 : =   0 ,     y 0 : =   ϕ .
s   : =   a i XOR   b i XOR   c i - 1 , c   : =   a i b i OR   a i c i - 1 OR   b i c i - 1 .
steps = n n + 1 .
S 0 = a ¯ b + a b ¯ , C 0 = ab ;
S 1 = ab + a ¯ b ¯ , C 1 = a + b .
S 0 out = C 0 in ¯ S 0 + C 0 in S 1 , C 0 out = C 0 in ¯ C 0 + C 0 in C 1 , S 1 out = C 1 in ¯ S 0 + C 1 in S 1 , C 1 out = C 1 in ¯ C 0 + C 1 in C 1 .
steps = n ld   n + 3 .
steps = n n + 1 .
throughput   Θ = no .   parallel   calculations no .   steps   per   one   iteration = p s .
Θ bpRCA / bs = Θ bpRCA Θ bs = A bs A bpRCA 1 ld   n + n = ρ   1 n + ld   n ,
Θ bpCS / bs = Θ bpCS Θ bs = A bs A bpCS ld   n + n + 1 n + ld   n ld n + ld   n + 3 = σ   ld   n + n + 1 n + ld   n ld n + ld   n + 3 ,
Θ bpRCA / bpCS = Θ bpRCA Θ bpCS = A bpCS A bpRCA ld n + ld   n + 3 ld   n + n + 1 = τ   ld n + ld   n + 3 ld   n + n + 1 .
P = 60   1 33   1 / clock   cycle .

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