Abstract

The wormhole adaptive recovery-based routing via pre-emption (WARRP) core optoelectronic chip, which integrates core deadlock-handling circuitry for a fully adaptive deadlock-free multiprocessor network router, is presented. This chip demonstrates primarily the integration of complex deadlock-recovery circuitry and free-space optoelectronic input–output on a monolithic GaAs-based chip. The design and implementation of the first-generation, bit-serial, torus-connected chip that uses 1400 transistors and six light-emitting diode–photodetector pairs is presented.

© 1998 Optical Society of America

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    [CrossRef]
  25. K. V. Anjan, T. M. Pinkston, “DISHA: a deadlock recovery scheme for fully adaptive routing,” in Proceedings of the Ninth International Parallel Processing Symposium, Santa Barbara, Calif. (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 537–543.
    [CrossRef]
  26. K. V. Anjan, T. M. Pinkston, J. Duato, “Generalized theory for deadlock-free adaptive wormhole routing and its application to DISHA concurrent,” in Proceedings of the Tenth International Parallel Processing Symposium, Honolulu, Haw. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 815–821.

1997

T. K. Woodward, A. L. Lentine, K. W. Goossen, J. A. Walker, B. T. Tseng, S. P. Hui, J. Lothian, R. E. Leibenguth, “Demultiplexing 2.48-Gb/s optical signals with a CMOS receiver array based on clocked-sense-amplifier,” IEEE Photon. Technol. Lett. 9, 1146–1148 (1997).
[CrossRef]

T. M. Pinkston, C. Kuznia, “Smart-pixel-based network interface chip,” Appl. Opt. 36, 4871–4880 (1997).
[CrossRef] [PubMed]

1996

1995

M. A. Neifeld, J. D. Hayes, “Error correction schemes for volume optical memories,” Appl. Opt. 34, 8183–8191 (1995).
[CrossRef] [PubMed]

D. S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, S. Wilkinson, M. Lee, N. M. Jokerest, M. Brooke, “A fine-grain, high-throughput architecture using through-wafer optical interconnect,” J. Lightwave Technol. 13, 1085–1092 (1995).
[CrossRef]

1994

1993

L. M. Ni, P. K. McKinley, “A survey of wormhole routing techniques in direct networks,” IEEE Comput. 26, 62–76 (1993).
[CrossRef]

J. Duato, “A new theory of deadlock-free adaptive routing in wormhole networks,” IEEE Trans. Parallel Distribut. Syst. 4, 1320–1331 (1993).
[CrossRef]

1992

W. J. Dally, “Virtual-channel flow control,” IEEE Trans. Parallel Distribut. Syst. 3, 194–205 (1992).
[CrossRef]

1990

W. J. Dally, “Performance analysis of k-ary n-cube interconnection networks,” IEEE Trans. Comput. 39, 775–785 (1990).
[CrossRef]

1987

W. J. Dally, C. L. Seitz, “Deadlock-free message routing in multiprocessor interconnection networks,” IEEE Trans. Comput. 36, 547–553 (1987).
[CrossRef]

Amano, C.

Anjan, K. V.

K. V. Anjan, T. M. Pinkston, “An efficient, fully adaptive deadlock recovery scheme: DISHA,” in Proceedings of the Twenty-Second International Symposium on Computer Architecture, Santa Margherita Ligure, Italy (Association for Computing Machinery, New York, 1995), pp. 201–210.

K. V. Anjan, T. M. Pinkston, “DISHA: a deadlock recovery scheme for fully adaptive routing,” in Proceedings of the Ninth International Parallel Processing Symposium, Santa Barbara, Calif. (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 537–543.
[CrossRef]

K. V. Anjan, T. M. Pinkston, J. Duato, “Generalized theory for deadlock-free adaptive wormhole routing and its application to DISHA concurrent,” in Proceedings of the Tenth International Parallel Processing Symposium, Honolulu, Haw. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 815–821.

Ateno, K.

S. Matsuo, K. Ateno, T. Kurokawa, “VCSEL-based smart pixel,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 19–21.

Beckman, M. G.

Beyette, F. R.

P. J. Stanko, F. R. Beyette, E. M. Hayes, R. D. Snyder, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, “An optoelectronic recirculating sorter based on CMOS/VCSEL smart pixel array: architecture and system demonstration,” in Proceedings of the 1996 International Topical Meeting on Optical Computing (IEEE Lasers and Electro-Optics Society, Piscataway, N.J., 1996), Vol. 1, pp. 86–89.

Bounnak, S.

Y. Liu, M. Hibbs-Brenner, B. Morgan, J. Nohava, B. Walterson, T. Marta, S. Bounnak, E. Kalweit, J. Lehman, D. Carlson, P. Wilson, “Integrated VCSEL’s, MSM photodetectors, and GaAs MESFET’s for low cost optical interconnects,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 22–24.

Brooke, M.

D. S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, S. Wilkinson, M. Lee, N. M. Jokerest, M. Brooke, “A fine-grain, high-throughput architecture using through-wafer optical interconnect,” J. Lightwave Technol. 13, 1085–1092 (1995).
[CrossRef]

Buchanan, B.

D. S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, S. Wilkinson, M. Lee, N. M. Jokerest, M. Brooke, “A fine-grain, high-throughput architecture using through-wafer optical interconnect,” J. Lightwave Technol. 13, 1085–1092 (1995).
[CrossRef]

Camperi-Ginestet, C.

D. S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, S. Wilkinson, M. Lee, N. M. Jokerest, M. Brooke, “A fine-grain, high-throughput architecture using through-wafer optical interconnect,” J. Lightwave Technol. 13, 1085–1092 (1995).
[CrossRef]

Carlson, D.

Y. Liu, M. Hibbs-Brenner, B. Morgan, J. Nohava, B. Walterson, T. Marta, S. Bounnak, E. Kalweit, J. Lehman, D. Carlson, P. Wilson, “Integrated VCSEL’s, MSM photodetectors, and GaAs MESFET’s for low cost optical interconnects,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 22–24.

Cloonan, T. J.

Crisci, R. J.

Cunningham, J. E.

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

Dally, W. J.

W. J. Dally, “Virtual-channel flow control,” IEEE Trans. Parallel Distribut. Syst. 3, 194–205 (1992).
[CrossRef]

W. J. Dally, “Performance analysis of k-ary n-cube interconnection networks,” IEEE Trans. Comput. 39, 775–785 (1990).
[CrossRef]

W. J. Dally, C. L. Seitz, “Deadlock-free message routing in multiprocessor interconnection networks,” IEEE Trans. Comput. 36, 547–553 (1987).
[CrossRef]

Duato, J.

J. Duato, “A new theory of deadlock-free adaptive routing in wormhole networks,” IEEE Trans. Parallel Distribut. Syst. 4, 1320–1331 (1993).
[CrossRef]

K. V. Anjan, T. M. Pinkston, J. Duato, “Generalized theory for deadlock-free adaptive wormhole routing and its application to DISHA concurrent,” in Proceedings of the Tenth International Parallel Processing Symposium, Honolulu, Haw. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 815–821.

Feld, S. A.

P. J. Stanko, F. R. Beyette, E. M. Hayes, R. D. Snyder, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, “An optoelectronic recirculating sorter based on CMOS/VCSEL smart pixel array: architecture and system demonstration,” in Proceedings of the 1996 International Topical Meeting on Optical Computing (IEEE Lasers and Electro-Optics Society, Piscataway, N.J., 1996), Vol. 1, pp. 86–89.

Ford, J. E.

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

Goossen, K. W.

T. K. Woodward, A. L. Lentine, K. W. Goossen, J. A. Walker, B. T. Tseng, S. P. Hui, J. Lothian, R. E. Leibenguth, “Demultiplexing 2.48-Gb/s optical signals with a CMOS receiver array based on clocked-sense-amplifier,” IEEE Photon. Technol. Lett. 9, 1146–1148 (1997).
[CrossRef]

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

Hayes, E. M.

P. J. Stanko, F. R. Beyette, E. M. Hayes, R. D. Snyder, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, “An optoelectronic recirculating sorter based on CMOS/VCSEL smart pixel array: architecture and system demonstration,” in Proceedings of the 1996 International Topical Meeting on Optical Computing (IEEE Lasers and Electro-Optics Society, Piscataway, N.J., 1996), Vol. 1, pp. 86–89.

Hayes, J. D.

Hibbs-Brenner, M.

Y. Liu, M. Hibbs-Brenner, B. Morgan, J. Nohava, B. Walterson, T. Marta, S. Bounnak, E. Kalweit, J. Lehman, D. Carlson, P. Wilson, “Integrated VCSEL’s, MSM photodetectors, and GaAs MESFET’s for low cost optical interconnects,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 22–24.

Hinterlong, S. J.

Hinton, H. S.

F. B. McCormick, T. J. Cloonan, A. L. Lentine, J. M. Sasian, R. L. Morrison, M. G. Beckman, S. L. Walker, M. J. Wojcik, S. J. Hinterlong, R. J. Crisci, R. A. Novotny, H. S. Hinton, “Five-stage free-space optical switching network with field-effect transistor self-electro-optic-effect device smart-pixel arrays,” Appl. Opt. 33, 1601–1618 (1994).
[CrossRef] [PubMed]

H. S. Hinton, “Intelligent optical backplanes,” in Proceedings of the Second International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 133–143.
[CrossRef]

S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the LEOS 1996 Summer Topical Meeting on Smart Pixels (IEEE Lasers and Electro-Optics Society, Piscataway, N.J., 1996), pp. 159–161.

Hui, S. P.

T. K. Woodward, A. L. Lentine, K. W. Goossen, J. A. Walker, B. T. Tseng, S. P. Hui, J. Lothian, R. E. Leibenguth, “Demultiplexing 2.48-Gb/s optical signals with a CMOS receiver array based on clocked-sense-amplifier,” IEEE Photon. Technol. Lett. 9, 1146–1148 (1997).
[CrossRef]

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

Jan, W. Y.

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

Jokerest, N. M.

D. S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, S. Wilkinson, M. Lee, N. M. Jokerest, M. Brooke, “A fine-grain, high-throughput architecture using through-wafer optical interconnect,” J. Lightwave Technol. 13, 1085–1092 (1995).
[CrossRef]

Kalweit, E.

Y. Liu, M. Hibbs-Brenner, B. Morgan, J. Nohava, B. Walterson, T. Marta, S. Bounnak, E. Kalweit, J. Lehman, D. Carlson, P. Wilson, “Integrated VCSEL’s, MSM photodetectors, and GaAs MESFET’s for low cost optical interconnects,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 22–24.

Kiamilev, F. E.

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

F. E. Kiamilev, J. S. Lambirth, R. G. Rozier, A. V. Krishnamoorthy, “Design of a 64-bit, 100 MIPS microprocessor core IC for hybrid CMOS-SEED technology,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 53–60.
[CrossRef]

Krishnamoorthy, A. V.

F. E. Kiamilev, J. S. Lambirth, R. G. Rozier, A. V. Krishnamoorthy, “Design of a 64-bit, 100 MIPS microprocessor core IC for hybrid CMOS-SEED technology,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 53–60.
[CrossRef]

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

Kurokawa, T.

M. Yamaguchi, T. Yamamoto, K. I. Yukimatsu, S. Matsuo, C. Amano, Y. Nakao, T. Kurokawa, “Experimental investigation of a digital free-space photonic switch that uses exciton absorption switch arrays,” Appl. Opt. 33, 1337–1344 (1994).
[CrossRef] [PubMed]

S. Matsuo, K. Ateno, T. Kurokawa, “VCSEL-based smart pixel,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 19–21.

Kuznia, C.

Lacy, W. S.

D. S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, S. Wilkinson, M. Lee, N. M. Jokerest, M. Brooke, “A fine-grain, high-throughput architecture using through-wafer optical interconnect,” J. Lightwave Technol. 13, 1085–1092 (1995).
[CrossRef]

Lambirth, J. S.

F. E. Kiamilev, J. S. Lambirth, R. G. Rozier, A. V. Krishnamoorthy, “Design of a 64-bit, 100 MIPS microprocessor core IC for hybrid CMOS-SEED technology,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 53–60.
[CrossRef]

Lane, B.

Lee, M.

D. S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, S. Wilkinson, M. Lee, N. M. Jokerest, M. Brooke, “A fine-grain, high-throughput architecture using through-wafer optical interconnect,” J. Lightwave Technol. 13, 1085–1092 (1995).
[CrossRef]

Lehman, J.

Y. Liu, M. Hibbs-Brenner, B. Morgan, J. Nohava, B. Walterson, T. Marta, S. Bounnak, E. Kalweit, J. Lehman, D. Carlson, P. Wilson, “Integrated VCSEL’s, MSM photodetectors, and GaAs MESFET’s for low cost optical interconnects,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 22–24.

Leibenguth, R. E.

T. K. Woodward, A. L. Lentine, K. W. Goossen, J. A. Walker, B. T. Tseng, S. P. Hui, J. Lothian, R. E. Leibenguth, “Demultiplexing 2.48-Gb/s optical signals with a CMOS receiver array based on clocked-sense-amplifier,” IEEE Photon. Technol. Lett. 9, 1146–1148 (1997).
[CrossRef]

Lentine, A. L.

T. K. Woodward, A. L. Lentine, K. W. Goossen, J. A. Walker, B. T. Tseng, S. P. Hui, J. Lothian, R. E. Leibenguth, “Demultiplexing 2.48-Gb/s optical signals with a CMOS receiver array based on clocked-sense-amplifier,” IEEE Photon. Technol. Lett. 9, 1146–1148 (1997).
[CrossRef]

F. B. McCormick, T. J. Cloonan, A. L. Lentine, J. M. Sasian, R. L. Morrison, M. G. Beckman, S. L. Walker, M. J. Wojcik, S. J. Hinterlong, R. J. Crisci, R. A. Novotny, H. S. Hinton, “Five-stage free-space optical switching network with field-effect transistor self-electro-optic-effect device smart-pixel arrays,” Appl. Opt. 33, 1601–1618 (1994).
[CrossRef] [PubMed]

Liu, Y.

Y. Liu, M. Hibbs-Brenner, B. Morgan, J. Nohava, B. Walterson, T. Marta, S. Bounnak, E. Kalweit, J. Lehman, D. Carlson, P. Wilson, “Integrated VCSEL’s, MSM photodetectors, and GaAs MESFET’s for low cost optical interconnects,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 22–24.

Lothian, J.

T. K. Woodward, A. L. Lentine, K. W. Goossen, J. A. Walker, B. T. Tseng, S. P. Hui, J. Lothian, R. E. Leibenguth, “Demultiplexing 2.48-Gb/s optical signals with a CMOS receiver array based on clocked-sense-amplifier,” IEEE Photon. Technol. Lett. 9, 1146–1148 (1997).
[CrossRef]

Marta, T.

Y. Liu, M. Hibbs-Brenner, B. Morgan, J. Nohava, B. Walterson, T. Marta, S. Bounnak, E. Kalweit, J. Lehman, D. Carlson, P. Wilson, “Integrated VCSEL’s, MSM photodetectors, and GaAs MESFET’s for low cost optical interconnects,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 22–24.

Martin, R.

Matsuo, S.

M. Yamaguchi, T. Yamamoto, K. I. Yukimatsu, S. Matsuo, C. Amano, Y. Nakao, T. Kurokawa, “Experimental investigation of a digital free-space photonic switch that uses exciton absorption switch arrays,” Appl. Opt. 33, 1337–1344 (1994).
[CrossRef] [PubMed]

S. Matsuo, K. Ateno, T. Kurokawa, “VCSEL-based smart pixel,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 19–21.

McCormick, F. B.

McKinley, P. K.

L. M. Ni, P. K. McKinley, “A survey of wormhole routing techniques in direct networks,” IEEE Comput. 26, 62–76 (1993).
[CrossRef]

Miller, D. A. B.

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

Mitkas, P. A.

P. J. Stanko, F. R. Beyette, E. M. Hayes, R. D. Snyder, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, “An optoelectronic recirculating sorter based on CMOS/VCSEL smart pixel array: architecture and system demonstration,” in Proceedings of the 1996 International Topical Meeting on Optical Computing (IEEE Lasers and Electro-Optics Society, Piscataway, N.J., 1996), Vol. 1, pp. 86–89.

Morgan, B.

Y. Liu, M. Hibbs-Brenner, B. Morgan, J. Nohava, B. Walterson, T. Marta, S. Bounnak, E. Kalweit, J. Lehman, D. Carlson, P. Wilson, “Integrated VCSEL’s, MSM photodetectors, and GaAs MESFET’s for low cost optical interconnects,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 22–24.

Morrison, R. L.

Nakao, Y.

Neifeld, M. A.

Ni, L. M.

L. M. Ni, P. K. McKinley, “A survey of wormhole routing techniques in direct networks,” IEEE Comput. 26, 62–76 (1993).
[CrossRef]

Nohava, J.

Y. Liu, M. Hibbs-Brenner, B. Morgan, J. Nohava, B. Walterson, T. Marta, S. Bounnak, E. Kalweit, J. Lehman, D. Carlson, P. Wilson, “Integrated VCSEL’s, MSM photodetectors, and GaAs MESFET’s for low cost optical interconnects,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 22–24.

Novotny, R. A.

Nuss, M. C.

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

Pinkston, T. M.

T. M. Pinkston, C. Kuznia, “Smart-pixel-based network interface chip,” Appl. Opt. 36, 4871–4880 (1997).
[CrossRef] [PubMed]

M. Raksapatcharawong, T. M. Pinkston, “An optical interconnect model for k-ary n-cube wormhole networks,” in Proceedings of the Tenth International Parallel Processing Symposium, Honolulu, Haw. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 666–672.

T. M. Pinkston, S. Warnakulasuriya, “On deadlocks in interconnection networks,” in Proceedings of the Twenty-Fourth International Symposium on Computer Architecture (Association for Computing Machinery, New York, 1997), pp. 38–49.
[CrossRef]

K. V. Anjan, T. M. Pinkston, “An efficient, fully adaptive deadlock recovery scheme: DISHA,” in Proceedings of the Twenty-Second International Symposium on Computer Architecture, Santa Margherita Ligure, Italy (Association for Computing Machinery, New York, 1995), pp. 201–210.

K. V. Anjan, T. M. Pinkston, J. Duato, “Generalized theory for deadlock-free adaptive wormhole routing and its application to DISHA concurrent,” in Proceedings of the Tenth International Parallel Processing Symposium, Honolulu, Haw. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 815–821.

K. V. Anjan, T. M. Pinkston, “DISHA: a deadlock recovery scheme for fully adaptive routing,” in Proceedings of the Ninth International Parallel Processing Symposium, Santa Barbara, Calif. (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 537–543.
[CrossRef]

Raksapatcharawong, M.

M. Raksapatcharawong, T. M. Pinkston, “An optical interconnect model for k-ary n-cube wormhole networks,” in Proceedings of the Tenth International Parallel Processing Symposium, Honolulu, Haw. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 666–672.

Ressler, E. K.

A. H. Sayles, B. L. Shoop, E. K. Ressler, “A novel smart pixel network for signal processing applications,” in Proceedings of the LEOS 1996 Summer Topical Meeting on Smart Pixels (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 86–87.

Ritter, K. J.

Rozier, R. G.

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

F. E. Kiamilev, J. S. Lambirth, R. G. Rozier, A. V. Krishnamoorthy, “Design of a 64-bit, 100 MIPS microprocessor core IC for hybrid CMOS-SEED technology,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 53–60.
[CrossRef]

Sasian, J. M.

Sayles, A. H.

A. H. Sayles, B. L. Shoop, E. K. Ressler, “A novel smart pixel network for signal processing applications,” in Proceedings of the LEOS 1996 Summer Topical Meeting on Smart Pixels (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 86–87.

Seitz, C. L.

W. J. Dally, C. L. Seitz, “Deadlock-free message routing in multiprocessor interconnection networks,” IEEE Trans. Comput. 36, 547–553 (1987).
[CrossRef]

Sherif, S. S.

S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the LEOS 1996 Summer Topical Meeting on Smart Pixels (IEEE Lasers and Electro-Optics Society, Piscataway, N.J., 1996), pp. 159–161.

Shoop, B. L.

A. H. Sayles, B. L. Shoop, E. K. Ressler, “A novel smart pixel network for signal processing applications,” in Proceedings of the LEOS 1996 Summer Topical Meeting on Smart Pixels (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 86–87.

Snyder, R. D.

P. J. Stanko, F. R. Beyette, E. M. Hayes, R. D. Snyder, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, “An optoelectronic recirculating sorter based on CMOS/VCSEL smart pixel array: architecture and system demonstration,” in Proceedings of the 1996 International Topical Meeting on Optical Computing (IEEE Lasers and Electro-Optics Society, Piscataway, N.J., 1996), Vol. 1, pp. 86–89.

Stanko, P. J.

P. J. Stanko, F. R. Beyette, E. M. Hayes, R. D. Snyder, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, “An optoelectronic recirculating sorter based on CMOS/VCSEL smart pixel array: architecture and system demonstration,” in Proceedings of the 1996 International Topical Meeting on Optical Computing (IEEE Lasers and Electro-Optics Society, Piscataway, N.J., 1996), Vol. 1, pp. 86–89.

Szymanski, T. H.

S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the LEOS 1996 Summer Topical Meeting on Smart Pixels (IEEE Lasers and Electro-Optics Society, Piscataway, N.J., 1996), pp. 159–161.

Tseng, B.

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

Tseng, B. T.

T. K. Woodward, A. L. Lentine, K. W. Goossen, J. A. Walker, B. T. Tseng, S. P. Hui, J. Lothian, R. E. Leibenguth, “Demultiplexing 2.48-Gb/s optical signals with a CMOS receiver array based on clocked-sense-amplifier,” IEEE Photon. Technol. Lett. 9, 1146–1148 (1997).
[CrossRef]

Walker, J. A.

T. K. Woodward, A. L. Lentine, K. W. Goossen, J. A. Walker, B. T. Tseng, S. P. Hui, J. Lothian, R. E. Leibenguth, “Demultiplexing 2.48-Gb/s optical signals with a CMOS receiver array based on clocked-sense-amplifier,” IEEE Photon. Technol. Lett. 9, 1146–1148 (1997).
[CrossRef]

Walker, J. W.

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

Walker, S. L.

Walterson, B.

Y. Liu, M. Hibbs-Brenner, B. Morgan, J. Nohava, B. Walterson, T. Marta, S. Bounnak, E. Kalweit, J. Lehman, D. Carlson, P. Wilson, “Integrated VCSEL’s, MSM photodetectors, and GaAs MESFET’s for low cost optical interconnects,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 22–24.

Warnakulasuriya, S.

T. M. Pinkston, S. Warnakulasuriya, “On deadlocks in interconnection networks,” in Proceedings of the Twenty-Fourth International Symposium on Computer Architecture (Association for Computing Machinery, New York, 1997), pp. 38–49.
[CrossRef]

Wilkinson, S.

D. S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, S. Wilkinson, M. Lee, N. M. Jokerest, M. Brooke, “A fine-grain, high-throughput architecture using through-wafer optical interconnect,” J. Lightwave Technol. 13, 1085–1092 (1995).
[CrossRef]

Wills, D. S.

D. S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, S. Wilkinson, M. Lee, N. M. Jokerest, M. Brooke, “A fine-grain, high-throughput architecture using through-wafer optical interconnect,” J. Lightwave Technol. 13, 1085–1092 (1995).
[CrossRef]

Wilmsen, C. W.

P. J. Stanko, F. R. Beyette, E. M. Hayes, R. D. Snyder, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, “An optoelectronic recirculating sorter based on CMOS/VCSEL smart pixel array: architecture and system demonstration,” in Proceedings of the 1996 International Topical Meeting on Optical Computing (IEEE Lasers and Electro-Optics Society, Piscataway, N.J., 1996), Vol. 1, pp. 86–89.

Wilson, P.

Y. Liu, M. Hibbs-Brenner, B. Morgan, J. Nohava, B. Walterson, T. Marta, S. Bounnak, E. Kalweit, J. Lehman, D. Carlson, P. Wilson, “Integrated VCSEL’s, MSM photodetectors, and GaAs MESFET’s for low cost optical interconnects,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 22–24.

Wojcik, M. J.

Woodward, T. K.

T. K. Woodward, A. L. Lentine, K. W. Goossen, J. A. Walker, B. T. Tseng, S. P. Hui, J. Lothian, R. E. Leibenguth, “Demultiplexing 2.48-Gb/s optical signals with a CMOS receiver array based on clocked-sense-amplifier,” IEEE Photon. Technol. Lett. 9, 1146–1148 (1997).
[CrossRef]

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

Worchesky, T. L.

Yamaguchi, M.

Yamamoto, T.

Yukimatsu, K. I.

Appl. Opt.

IEEE Comput.

L. M. Ni, P. K. McKinley, “A survey of wormhole routing techniques in direct networks,” IEEE Comput. 26, 62–76 (1993).
[CrossRef]

IEEE Photon. Technol. Lett.

T. K. Woodward, A. L. Lentine, K. W. Goossen, J. A. Walker, B. T. Tseng, S. P. Hui, J. Lothian, R. E. Leibenguth, “Demultiplexing 2.48-Gb/s optical signals with a CMOS receiver array based on clocked-sense-amplifier,” IEEE Photon. Technol. Lett. 9, 1146–1148 (1997).
[CrossRef]

IEEE Trans. Comput.

W. J. Dally, “Performance analysis of k-ary n-cube interconnection networks,” IEEE Trans. Comput. 39, 775–785 (1990).
[CrossRef]

W. J. Dally, C. L. Seitz, “Deadlock-free message routing in multiprocessor interconnection networks,” IEEE Trans. Comput. 36, 547–553 (1987).
[CrossRef]

IEEE Trans. Parallel Distribut. Syst.

J. Duato, “A new theory of deadlock-free adaptive routing in wormhole networks,” IEEE Trans. Parallel Distribut. Syst. 4, 1320–1331 (1993).
[CrossRef]

W. J. Dally, “Virtual-channel flow control,” IEEE Trans. Parallel Distribut. Syst. 3, 194–205 (1992).
[CrossRef]

J. Lightwave Technol.

D. S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, S. Wilkinson, M. Lee, N. M. Jokerest, M. Brooke, “A fine-grain, high-throughput architecture using through-wafer optical interconnect,” J. Lightwave Technol. 13, 1085–1092 (1995).
[CrossRef]

Other

F. E. Kiamilev, J. S. Lambirth, R. G. Rozier, A. V. Krishnamoorthy, “Design of a 64-bit, 100 MIPS microprocessor core IC for hybrid CMOS-SEED technology,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 53–60.
[CrossRef]

H. S. Hinton, “Intelligent optical backplanes,” in Proceedings of the Second International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 133–143.
[CrossRef]

S. S. Sherif, T. H. Szymanski, H. S. Hinton, “Design and implementation of a field programmable smart pixel array,” in Proceedings of the LEOS 1996 Summer Topical Meeting on Smart Pixels (IEEE Lasers and Electro-Optics Society, Piscataway, N.J., 1996), pp. 159–161.

M. Raksapatcharawong, T. M. Pinkston, “An optical interconnect model for k-ary n-cube wormhole networks,” in Proceedings of the Tenth International Parallel Processing Symposium, Honolulu, Haw. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 666–672.

T. M. Pinkston, S. Warnakulasuriya, “On deadlocks in interconnection networks,” in Proceedings of the Twenty-Fourth International Symposium on Computer Architecture (Association for Computing Machinery, New York, 1997), pp. 38–49.
[CrossRef]

K. V. Anjan, T. M. Pinkston, “An efficient, fully adaptive deadlock recovery scheme: DISHA,” in Proceedings of the Twenty-Second International Symposium on Computer Architecture, Santa Margherita Ligure, Italy (Association for Computing Machinery, New York, 1995), pp. 201–210.

Y. Liu, M. Hibbs-Brenner, B. Morgan, J. Nohava, B. Walterson, T. Marta, S. Bounnak, E. Kalweit, J. Lehman, D. Carlson, P. Wilson, “Integrated VCSEL’s, MSM photodetectors, and GaAs MESFET’s for low cost optical interconnects,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 22–24.

S. Matsuo, K. Ateno, T. Kurokawa, “VCSEL-based smart pixel,” in Spatial Light Modulators, Vol. of 1997 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1997), pp. 19–21.

Information can be found at http://web.mit.edu/fonstad/optochip/opto.home.html.

P. J. Stanko, F. R. Beyette, E. M. Hayes, R. D. Snyder, S. A. Feld, P. A. Mitkas, C. W. Wilmsen, “An optoelectronic recirculating sorter based on CMOS/VCSEL smart pixel array: architecture and system demonstration,” in Proceedings of the 1996 International Topical Meeting on Optical Computing (IEEE Lasers and Electro-Optics Society, Piscataway, N.J., 1996), Vol. 1, pp. 86–89.

A. H. Sayles, B. L. Shoop, E. K. Ressler, “A novel smart pixel network for signal processing applications,” in Proceedings of the LEOS 1996 Summer Topical Meeting on Smart Pixels (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 86–87.

A. V. Krishnamoorthy, J. E. Ford, K. W. Goossen, J. W. Walker, B. Tseng, S. P. Hui, J. E. Cunningham, W. Y. Jan, T. K. Woodward, M. C. Nuss, R. G. Rozier, F. E. Kiamilev, D. A. B. Miller, “The AMOEBA chip: an optoelectronic switch for multiprocessor networking using dense-WDM,” in Proceedings of the Third International Conference on Massively Parallel Processing Using Optical Interconnections (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 94–100 (1996).
[CrossRef]

K. V. Anjan, T. M. Pinkston, “DISHA: a deadlock recovery scheme for fully adaptive routing,” in Proceedings of the Ninth International Parallel Processing Symposium, Santa Barbara, Calif. (IEEE Computer Society, Los Alamitos, Calif., 1995), pp. 537–543.
[CrossRef]

K. V. Anjan, T. M. Pinkston, J. Duato, “Generalized theory for deadlock-free adaptive wormhole routing and its application to DISHA concurrent,” in Proceedings of the Tenth International Parallel Processing Symposium, Honolulu, Haw. (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 815–821.

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Figures (8)

Fig. 1
Fig. 1

Simple resource wait-for cycle that leads to deadlock. S’s, packet sources; D’s, packet destinations; C’s, channels; P’s, packets.

Fig. 2
Fig. 2

Illustration of progressive deadlock recovery routing

Fig. 3
Fig. 3

Block diagram of the WARRP router and the WARRP core components: OEI’s, optoelectronic interfaces; DM’s, demultiplexers; FC’s, flow controllers; IB’s, input virtual circuit buffers; MX’s, multiplexers; DB, deadlock buffer; OB’s, output virtual circuit buffers; EOI, electro-optic interface.

Fig. 4
Fig. 4

Concurrent deadlock-recovery operation with the WARRP core chip: (a) packet transmission over normal buffers, (b) deadlock-packet initiation and propagation over deadlock buffers. EFCL’s, external flow control logic.

Fig. 5
Fig. 5

Timing diagram for the WARRP core (circuit simulation).

Fig. 6
Fig. 6

Sequential deadlock-recovery operation with the WARRP core chip and the OMNI chip: (a) normal packet transmission, (b) deadlock-packet initiation and propagation over deadlock buffers.

Fig. 7
Fig. 7

Microphotograph of the WARRP core.

Fig. 8
Fig. 8

Fully functional microcontroller–field-programmable gate array (FPGA)–WARRP testing board.

Equations (1)

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T latency = T C n k - 1 2 + L W + T contention .

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