Abstract

Advances in VLSI and optoelectronic multichip module technologies are enabling the construction of ultracompact massively parallel processing systems. The technological parameters that define the wirability and delay characteristics of these technologies have a significant impact on the system architecture. An analytical model is presented that allows the design space exploration of the interconnection networks associated with multinode chips packaged on a single multichip module substrate. Possible system designs are evaluated for a two-level interconnect with separate k-ary n-cube networks for interchip and intrachip communication. The impact of several architectural and technological parameters on the optimal network implementation (based on average no-load latency) is analyzed.

© 1998 Optical Society of America

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    [CrossRef]
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    [CrossRef]
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    [CrossRef]
  33. R. A. Soref, F. Namavar, E. Cortesi, L. Friedman, R. Lareau, “Vertical 3-d integration of silicon waveguides in Si–SiO2–Si–SiO2–Si structure,” in Microelectronic Interconnects and Packages: Optical and Electrical Technologies, G. Arjavalingam, J. Pazaris, eds., Proc. SPIE1389, 408–421 (1990).
    [CrossRef]
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    [CrossRef] [PubMed]
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    [CrossRef] [PubMed]
  36. W. S. Lacy, J. L. Cruz-Rivera, D. S. Wills, “The offset cube: a three-dimensional multicomputer network topology using through-wafer optics,” IEEE Trans. Parallel Distribut. Syst. (to be published).

1997

D. S. Wills, H. H. Cat, J. L. Cruz-Rivera, W. S. Lacy, J. M. Baker, J. Eble, A. López-Lagunas, M. Hopper, “High throughput, low memory applications on the pica architecture,” IEEE Trans. Parallel Distrib. Syst. 8, 1055–1067 (1997).
[CrossRef]

1996

D. Basak, D. K. Panda, “Designing clustered multiprocessor systems under packaging and technological advancements,” IEEE Trans. Parallel Distribut. Syst. 7, 962–978 (1996).
[CrossRef]

1995

J. L. Cruz-Rivera, E. V. R. Di Bella, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Parallelized formulation of the maximum likelihood-expectation maximization algorithm for fine-grain message-passing architectures,” IEEE Trans. Med. Imag. 14, 758–762 (1995).
[CrossRef]

G. A. Sai-Halsz, “Performance trends in high-end processors,” Proc. IEEE 83, 20–36 (1995).
[CrossRef]

K. Aoyama, A. A. Chien, “The cost of adaptivity and virtual lanes in a wormhole router,” VLSI Design 2(4), 315–333 (1995).
[CrossRef]

D. C. Edelstein, G. A. Sai-Halsz, Y.-J. Mii, “VLSI on-chip interconnection performance simulations and measurements,” IBM J. Res. Develop. 39, 383–401 (1995).
[CrossRef]

J. Fan, B. Catanzaro, V. H. Ozguz, C. K. Cheng, S. H. Lee, “Design considerations and algorithms for partitioning opto-electronic multichip modules,” Appl. Opt. 34, 3116–3127 (1995).
[CrossRef] [PubMed]

1994

D. Zaleta, J. Fan, B. C. Kress, S. H. Lee, C. K. Cheng, “Optimum placement for optoelectronic multichip modules and the synthesis of diffractive optics for multichip module interconnects,” Appl. Opt. 33, 1444–1456 (1994).
[CrossRef] [PubMed]

L. J. Camp, R. Sharma, M. R. Feldman, “Guided-wave and free-space optical interconnects for parallel-processing systems: a comparison,” Appl. Opt. 33, 6168–6180 (1994).
[CrossRef] [PubMed]

J. Fan, B. Catanzaro, F. Kiamilev, S. C. Esener, S. H. Lee, “Architecture of an integrated computer-aided design system for optoelectronics,” Opt. Eng. 33, 1571–1580 (1994).
[CrossRef]

S. K. Patra, J. Ma, V. H. Ozguz, S. H. Lee, “Alignment issues in packaging for free-space optical interconnects,” Opt. Eng. 33, 1561–1570 (1994).
[CrossRef]

S. L. Scott, J. R. Goodman, “The impact of pipelined channels on k-ary n-cube networks,” IEEE Trans. Parallel Distribut. Syst. 5, 2–16 (1994).
[CrossRef]

1993

K. H. Calhoun, C. B. Camperi-Ginestet, N. M. Jokerst, “Vertical optical communication through stacked silicon wafers using hybrid monolithic thin film ingaasp emitters and detectors,” IEEE Photon. Technol. Lett. 5, 254–257 (1993).
[CrossRef]

1992

R. R. Tummala, “Multichip packaging—a tutorial,” Proc. IEEE 80, 1924–1941 (1992).
[CrossRef]

R. T. Chen, H. Lu, D. Robinson, M. Wang, G. Savant, T. Jannson, “Guided-wave planar optical interconnects using highly multiplexed polymer waveguide holograms,” J. Lightwave Technol. 10, 888–897 (1992).
[CrossRef]

1991

W. J. Dally, “Express (c)ubes: improving the performance of k-ary n-cube interconnection networks,” IEEE Trans. Comput. 40, 1016–1023 (1991).
[CrossRef]

A. Agarwal, “Limits on interconnection network performance,” IEEE Trans. Parallel Distribut. Syst. 2, 398–412 (1991).
[CrossRef]

S. Abraham, K. Padmanabhan, “Performance of multicomputer networks under pin-out constraints,” J. Parallel Distribut. Comput. 12, 237–248 (1991).
[CrossRef]

1990

W. J. Dally, “Performance analysis of k-ary n-cube interconnection networks,” IEEE Trans. Comput. 39, 775–785 (1990).
[CrossRef]

R. K. Kostuk, M. Kato, Y.-T. Huang, “Polarization properties of substrate mode holographic interconnects,” Appl. Opt. 29, 3848–3854 (1990).
[CrossRef] [PubMed]

1989

1988

Abraham, S.

S. Abraham, K. Padmanabhan, “Performance of multicomputer networks under pin-out constraints,” J. Parallel Distribut. Comput. 12, 237–248 (1991).
[CrossRef]

Agarwal, A.

A. Agarwal, “Limits on interconnection network performance,” IEEE Trans. Parallel Distribut. Syst. 2, 398–412 (1991).
[CrossRef]

Aoyama, K.

K. Aoyama, A. A. Chien, “The cost of adaptivity and virtual lanes in a wormhole router,” VLSI Design 2(4), 315–333 (1995).
[CrossRef]

Baker, J. M.

D. S. Wills, H. H. Cat, J. L. Cruz-Rivera, W. S. Lacy, J. M. Baker, J. Eble, A. López-Lagunas, M. Hopper, “High throughput, low memory applications on the pica architecture,” IEEE Trans. Parallel Distrib. Syst. 8, 1055–1067 (1997).
[CrossRef]

Bakoglu, H. B.

H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI (Addison-Wesley, Reading, Mass., 1990).

Basak, D.

D. Basak, D. K. Panda, “Designing clustered multiprocessor systems under packaging and technological advancements,” IEEE Trans. Parallel Distribut. Syst. 7, 962–978 (1996).
[CrossRef]

Brenner, K. H.

Calhoun, K. H.

K. H. Calhoun, C. B. Camperi-Ginestet, N. M. Jokerst, “Vertical optical communication through stacked silicon wafers using hybrid monolithic thin film ingaasp emitters and detectors,” IEEE Photon. Technol. Lett. 5, 254–257 (1993).
[CrossRef]

Camp, L. J.

Camperi-Ginestet, C. B.

K. H. Calhoun, C. B. Camperi-Ginestet, N. M. Jokerst, “Vertical optical communication through stacked silicon wafers using hybrid monolithic thin film ingaasp emitters and detectors,” IEEE Photon. Technol. Lett. 5, 254–257 (1993).
[CrossRef]

Cat, H. H.

D. S. Wills, H. H. Cat, J. L. Cruz-Rivera, W. S. Lacy, J. M. Baker, J. Eble, A. López-Lagunas, M. Hopper, “High throughput, low memory applications on the pica architecture,” IEEE Trans. Parallel Distrib. Syst. 8, 1055–1067 (1997).
[CrossRef]

Catanzaro, B.

J. Fan, B. Catanzaro, V. H. Ozguz, C. K. Cheng, S. H. Lee, “Design considerations and algorithms for partitioning opto-electronic multichip modules,” Appl. Opt. 34, 3116–3127 (1995).
[CrossRef] [PubMed]

J. Fan, B. Catanzaro, F. Kiamilev, S. C. Esener, S. H. Lee, “Architecture of an integrated computer-aided design system for optoelectronics,” Opt. Eng. 33, 1571–1580 (1994).
[CrossRef]

Chen, R. T.

R. T. Chen, H. Lu, D. Robinson, M. Wang, G. Savant, T. Jannson, “Guided-wave planar optical interconnects using highly multiplexed polymer waveguide holograms,” J. Lightwave Technol. 10, 888–897 (1992).
[CrossRef]

Cheng, C. K.

Chien, A. A.

K. Aoyama, A. A. Chien, “The cost of adaptivity and virtual lanes in a wormhole router,” VLSI Design 2(4), 315–333 (1995).
[CrossRef]

Cortesi, E.

R. A. Soref, F. Namavar, E. Cortesi, L. Friedman, R. Lareau, “Vertical 3-d integration of silicon waveguides in Si–SiO2–Si–SiO2–Si structure,” in Microelectronic Interconnects and Packages: Optical and Electrical Technologies, G. Arjavalingam, J. Pazaris, eds., Proc. SPIE1389, 408–421 (1990).
[CrossRef]

Cruz-Rivera, J. L.

D. S. Wills, H. H. Cat, J. L. Cruz-Rivera, W. S. Lacy, J. M. Baker, J. Eble, A. López-Lagunas, M. Hopper, “High throughput, low memory applications on the pica architecture,” IEEE Trans. Parallel Distrib. Syst. 8, 1055–1067 (1997).
[CrossRef]

J. L. Cruz-Rivera, E. V. R. Di Bella, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Parallelized formulation of the maximum likelihood-expectation maximization algorithm for fine-grain message-passing architectures,” IEEE Trans. Med. Imag. 14, 758–762 (1995).
[CrossRef]

J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Modeling the technology impact on the design of a two-level multicomputer interconnection network,” in Proceedings of the 1996 International Conference on Computer Design (IEEE Computer Society, Los Alamitos Calif., 1996), pp. 165–169.

J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Architectural desin issues for optoelectronic k-ary n-cube interconnection networks,” presented at the 1995 Optical Society of America Annual Meeting, Portland, Oregon, 10–15 September 1995.

J. L. Cruz-Rivera, W. S. Lacy, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Performance modeling of optical interconnection technologies for massively parallel processing systems,” in Proceedings of the Third International Workshop on Massively Parallel Processing Using Optical Interconnections, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos Calif., 1996), pp. 264–275.
[CrossRef]

W. S. Lacy, J. L. Cruz-Rivera, D. S. Wills, “The offset cube: a three-dimensional multicomputer network topology using through-wafer optics,” IEEE Trans. Parallel Distribut. Syst. (to be published).

Dally, W. J.

W. J. Dally, “Express (c)ubes: improving the performance of k-ary n-cube interconnection networks,” IEEE Trans. Comput. 40, 1016–1023 (1991).
[CrossRef]

W. J. Dally, “Performance analysis of k-ary n-cube interconnection networks,” IEEE Trans. Comput. 39, 775–785 (1990).
[CrossRef]

Di Bella, E. V. R.

J. L. Cruz-Rivera, E. V. R. Di Bella, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Parallelized formulation of the maximum likelihood-expectation maximization algorithm for fine-grain message-passing architectures,” IEEE Trans. Med. Imag. 14, 758–762 (1995).
[CrossRef]

Drabik, T. J.

Eble, J.

D. S. Wills, H. H. Cat, J. L. Cruz-Rivera, W. S. Lacy, J. M. Baker, J. Eble, A. López-Lagunas, M. Hopper, “High throughput, low memory applications on the pica architecture,” IEEE Trans. Parallel Distrib. Syst. 8, 1055–1067 (1997).
[CrossRef]

Edelstein, D. C.

D. C. Edelstein, G. A. Sai-Halsz, Y.-J. Mii, “VLSI on-chip interconnection performance simulations and measurements,” IBM J. Res. Develop. 39, 383–401 (1995).
[CrossRef]

Esener, S. C.

Fan, J.

Feldman, M. R.

Friedman, L.

R. A. Soref, F. Namavar, E. Cortesi, L. Friedman, R. Lareau, “Vertical 3-d integration of silicon waveguides in Si–SiO2–Si–SiO2–Si structure,” in Microelectronic Interconnects and Packages: Optical and Electrical Technologies, G. Arjavalingam, J. Pazaris, eds., Proc. SPIE1389, 408–421 (1990).
[CrossRef]

Gaylord, T. K.

J. L. Cruz-Rivera, E. V. R. Di Bella, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Parallelized formulation of the maximum likelihood-expectation maximization algorithm for fine-grain message-passing architectures,” IEEE Trans. Med. Imag. 14, 758–762 (1995).
[CrossRef]

J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Modeling the technology impact on the design of a two-level multicomputer interconnection network,” in Proceedings of the 1996 International Conference on Computer Design (IEEE Computer Society, Los Alamitos Calif., 1996), pp. 165–169.

J. L. Cruz-Rivera, W. S. Lacy, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Performance modeling of optical interconnection technologies for massively parallel processing systems,” in Proceedings of the Third International Workshop on Massively Parallel Processing Using Optical Interconnections, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos Calif., 1996), pp. 264–275.
[CrossRef]

J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Architectural desin issues for optoelectronic k-ary n-cube interconnection networks,” presented at the 1995 Optical Society of America Annual Meeting, Portland, Oregon, 10–15 September 1995.

Glytsis, E. N.

J. L. Cruz-Rivera, E. V. R. Di Bella, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Parallelized formulation of the maximum likelihood-expectation maximization algorithm for fine-grain message-passing architectures,” IEEE Trans. Med. Imag. 14, 758–762 (1995).
[CrossRef]

J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Modeling the technology impact on the design of a two-level multicomputer interconnection network,” in Proceedings of the 1996 International Conference on Computer Design (IEEE Computer Society, Los Alamitos Calif., 1996), pp. 165–169.

J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Architectural desin issues for optoelectronic k-ary n-cube interconnection networks,” presented at the 1995 Optical Society of America Annual Meeting, Portland, Oregon, 10–15 September 1995.

J. L. Cruz-Rivera, W. S. Lacy, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Performance modeling of optical interconnection technologies for massively parallel processing systems,” in Proceedings of the Third International Workshop on Massively Parallel Processing Using Optical Interconnections, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos Calif., 1996), pp. 264–275.
[CrossRef]

Goodman, J. R.

S. L. Scott, J. R. Goodman, “The impact of pipelined channels on k-ary n-cube networks,” IEEE Trans. Parallel Distribut. Syst. 5, 2–16 (1994).
[CrossRef]

Goodman, J. W.

J. W. Goodman, Introduction to Fourier Optics (McGraw-Hill, San Francisco, 1968).

Guest, C. C.

Hopper, M.

D. S. Wills, H. H. Cat, J. L. Cruz-Rivera, W. S. Lacy, J. M. Baker, J. Eble, A. López-Lagunas, M. Hopper, “High throughput, low memory applications on the pica architecture,” IEEE Trans. Parallel Distrib. Syst. 8, 1055–1067 (1997).
[CrossRef]

Huang, Y.-T.

Jannson, T.

R. T. Chen, H. Lu, D. Robinson, M. Wang, G. Savant, T. Jannson, “Guided-wave planar optical interconnects using highly multiplexed polymer waveguide holograms,” J. Lightwave Technol. 10, 888–897 (1992).
[CrossRef]

Jokerst, N. M.

K. H. Calhoun, C. B. Camperi-Ginestet, N. M. Jokerst, “Vertical optical communication through stacked silicon wafers using hybrid monolithic thin film ingaasp emitters and detectors,” IEEE Photon. Technol. Lett. 5, 254–257 (1993).
[CrossRef]

Kato, M.

Kiamilev, F.

J. Fan, B. Catanzaro, F. Kiamilev, S. C. Esener, S. H. Lee, “Architecture of an integrated computer-aided design system for optoelectronics,” Opt. Eng. 33, 1571–1580 (1994).
[CrossRef]

Kostuk, R. K.

Kress, B. C.

Lacy, W. S.

D. S. Wills, H. H. Cat, J. L. Cruz-Rivera, W. S. Lacy, J. M. Baker, J. Eble, A. López-Lagunas, M. Hopper, “High throughput, low memory applications on the pica architecture,” IEEE Trans. Parallel Distrib. Syst. 8, 1055–1067 (1997).
[CrossRef]

J. L. Cruz-Rivera, W. S. Lacy, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Performance modeling of optical interconnection technologies for massively parallel processing systems,” in Proceedings of the Third International Workshop on Massively Parallel Processing Using Optical Interconnections, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos Calif., 1996), pp. 264–275.
[CrossRef]

W. S. Lacy, J. L. Cruz-Rivera, D. S. Wills, “The offset cube: a three-dimensional multicomputer network topology using through-wafer optics,” IEEE Trans. Parallel Distribut. Syst. (to be published).

Lareau, R.

R. A. Soref, F. Namavar, E. Cortesi, L. Friedman, R. Lareau, “Vertical 3-d integration of silicon waveguides in Si–SiO2–Si–SiO2–Si structure,” in Microelectronic Interconnects and Packages: Optical and Electrical Technologies, G. Arjavalingam, J. Pazaris, eds., Proc. SPIE1389, 408–421 (1990).
[CrossRef]

Lee, S. H.

López-Lagunas, A.

D. S. Wills, H. H. Cat, J. L. Cruz-Rivera, W. S. Lacy, J. M. Baker, J. Eble, A. López-Lagunas, M. Hopper, “High throughput, low memory applications on the pica architecture,” IEEE Trans. Parallel Distrib. Syst. 8, 1055–1067 (1997).
[CrossRef]

Lu, H.

R. T. Chen, H. Lu, D. Robinson, M. Wang, G. Savant, T. Jannson, “Guided-wave planar optical interconnects using highly multiplexed polymer waveguide holograms,” J. Lightwave Technol. 10, 888–897 (1992).
[CrossRef]

Ma, J.

S. K. Patra, J. Ma, V. H. Ozguz, S. H. Lee, “Alignment issues in packaging for free-space optical interconnects,” Opt. Eng. 33, 1561–1570 (1994).
[CrossRef]

Mii, Y.-J.

D. C. Edelstein, G. A. Sai-Halsz, Y.-J. Mii, “VLSI on-chip interconnection performance simulations and measurements,” IBM J. Res. Develop. 39, 383–401 (1995).
[CrossRef]

Namavar, F.

R. A. Soref, F. Namavar, E. Cortesi, L. Friedman, R. Lareau, “Vertical 3-d integration of silicon waveguides in Si–SiO2–Si–SiO2–Si structure,” in Microelectronic Interconnects and Packages: Optical and Electrical Technologies, G. Arjavalingam, J. Pazaris, eds., Proc. SPIE1389, 408–421 (1990).
[CrossRef]

Ozguz, V. H.

J. Fan, B. Catanzaro, V. H. Ozguz, C. K. Cheng, S. H. Lee, “Design considerations and algorithms for partitioning opto-electronic multichip modules,” Appl. Opt. 34, 3116–3127 (1995).
[CrossRef] [PubMed]

S. K. Patra, J. Ma, V. H. Ozguz, S. H. Lee, “Alignment issues in packaging for free-space optical interconnects,” Opt. Eng. 33, 1561–1570 (1994).
[CrossRef]

Padmanabhan, K.

S. Abraham, K. Padmanabhan, “Performance of multicomputer networks under pin-out constraints,” J. Parallel Distribut. Comput. 12, 237–248 (1991).
[CrossRef]

Panda, D. K.

D. Basak, D. K. Panda, “Designing clustered multiprocessor systems under packaging and technological advancements,” IEEE Trans. Parallel Distribut. Syst. 7, 962–978 (1996).
[CrossRef]

Patra, S. K.

S. K. Patra, J. Ma, V. H. Ozguz, S. H. Lee, “Alignment issues in packaging for free-space optical interconnects,” Opt. Eng. 33, 1561–1570 (1994).
[CrossRef]

Pinkston, T. M.

M. Raksapatcharawong, T. M. Pinkston, “An optical interconnect model for k-ary n-cube wormhole networks,” in Proceedings of the Tenth International Parallel Processing Symposium (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 666–672.

Raksapatcharawong, M.

M. Raksapatcharawong, T. M. Pinkston, “An optical interconnect model for k-ary n-cube wormhole networks,” in Proceedings of the Tenth International Parallel Processing Symposium (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 666–672.

Robinson, D.

R. T. Chen, H. Lu, D. Robinson, M. Wang, G. Savant, T. Jannson, “Guided-wave planar optical interconnects using highly multiplexed polymer waveguide holograms,” J. Lightwave Technol. 10, 888–897 (1992).
[CrossRef]

Sai-Halsz, G. A.

D. C. Edelstein, G. A. Sai-Halsz, Y.-J. Mii, “VLSI on-chip interconnection performance simulations and measurements,” IBM J. Res. Develop. 39, 383–401 (1995).
[CrossRef]

G. A. Sai-Halsz, “Performance trends in high-end processors,” Proc. IEEE 83, 20–36 (1995).
[CrossRef]

Sauer, F.

Savant, G.

R. T. Chen, H. Lu, D. Robinson, M. Wang, G. Savant, T. Jannson, “Guided-wave planar optical interconnects using highly multiplexed polymer waveguide holograms,” J. Lightwave Technol. 10, 888–897 (1992).
[CrossRef]

Scott, S. L.

S. L. Scott, J. R. Goodman, “The impact of pipelined channels on k-ary n-cube networks,” IEEE Trans. Parallel Distribut. Syst. 5, 2–16 (1994).
[CrossRef]

Sferrino, V. J.

V. J. Sferrino, “Multichip module study,” Tech. Rep. TR9545 (MIT Lincoln Laboratory, Lexington, Mass. 1992).

Sharma, R.

Soref, R. A.

R. A. Soref, F. Namavar, E. Cortesi, L. Friedman, R. Lareau, “Vertical 3-d integration of silicon waveguides in Si–SiO2–Si–SiO2–Si structure,” in Microelectronic Interconnects and Packages: Optical and Electrical Technologies, G. Arjavalingam, J. Pazaris, eds., Proc. SPIE1389, 408–421 (1990).
[CrossRef]

Tummala, R. R.

R. R. Tummala, “Multichip packaging—a tutorial,” Proc. IEEE 80, 1924–1941 (1992).
[CrossRef]

Wang, M.

R. T. Chen, H. Lu, D. Robinson, M. Wang, G. Savant, T. Jannson, “Guided-wave planar optical interconnects using highly multiplexed polymer waveguide holograms,” J. Lightwave Technol. 10, 888–897 (1992).
[CrossRef]

Wills, D. S.

D. S. Wills, H. H. Cat, J. L. Cruz-Rivera, W. S. Lacy, J. M. Baker, J. Eble, A. López-Lagunas, M. Hopper, “High throughput, low memory applications on the pica architecture,” IEEE Trans. Parallel Distrib. Syst. 8, 1055–1067 (1997).
[CrossRef]

J. L. Cruz-Rivera, E. V. R. Di Bella, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Parallelized formulation of the maximum likelihood-expectation maximization algorithm for fine-grain message-passing architectures,” IEEE Trans. Med. Imag. 14, 758–762 (1995).
[CrossRef]

J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Modeling the technology impact on the design of a two-level multicomputer interconnection network,” in Proceedings of the 1996 International Conference on Computer Design (IEEE Computer Society, Los Alamitos Calif., 1996), pp. 165–169.

J. L. Cruz-Rivera, W. S. Lacy, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Performance modeling of optical interconnection technologies for massively parallel processing systems,” in Proceedings of the Third International Workshop on Massively Parallel Processing Using Optical Interconnections, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos Calif., 1996), pp. 264–275.
[CrossRef]

J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Architectural desin issues for optoelectronic k-ary n-cube interconnection networks,” presented at the 1995 Optical Society of America Annual Meeting, Portland, Oregon, 10–15 September 1995.

W. S. Lacy, J. L. Cruz-Rivera, D. S. Wills, “The offset cube: a three-dimensional multicomputer network topology using through-wafer optics,” IEEE Trans. Parallel Distribut. Syst. (to be published).

Zaleta, D.

Appl. Opt.

M. R. Feldman, S. C. Esener, C. C. Guest, S. H. Lee, “Comparison between optical and electrical interconnects based on power and speed considerations,” Appl. Opt. 27, 1742–1751 (1988).
[CrossRef] [PubMed]

K. H. Brenner, F. Sauer, “Diffractive–reflective optical interconnects,” Appl. Opt. 27, 4251–4254 (1988).
[CrossRef] [PubMed]

F. Sauer, “Fabrication of diffractive–reflective optical interconnects for infrared operation based on total internal reflection,” Appl. Opt. 28, 386–388 (1989).
[CrossRef] [PubMed]

M. R. Feldman, C. C. Guest, “Interconnect density capabilities of computer generated holograms for optical interconnections of VLSI circuits,” Appl. Opt. 28, 3134–3137 (1989).
[CrossRef] [PubMed]

M. R. Feldman, C. C. Guest, T. J. Drabik, S. C. Esener, “Comparison between electrical and free-space optical interconnections for fine-grain processor arrays based on interconnect density capabilities,” Appl. Opt. 28, 3820–3829 (1989).
[CrossRef] [PubMed]

R. K. Kostuk, M. Kato, Y.-T. Huang, “Polarization properties of substrate mode holographic interconnects,” Appl. Opt. 29, 3848–3854 (1990).
[CrossRef] [PubMed]

D. Zaleta, J. Fan, B. C. Kress, S. H. Lee, C. K. Cheng, “Optimum placement for optoelectronic multichip modules and the synthesis of diffractive optics for multichip module interconnects,” Appl. Opt. 33, 1444–1456 (1994).
[CrossRef] [PubMed]

L. J. Camp, R. Sharma, M. R. Feldman, “Guided-wave and free-space optical interconnects for parallel-processing systems: a comparison,” Appl. Opt. 33, 6168–6180 (1994).
[CrossRef] [PubMed]

J. Fan, B. Catanzaro, V. H. Ozguz, C. K. Cheng, S. H. Lee, “Design considerations and algorithms for partitioning opto-electronic multichip modules,” Appl. Opt. 34, 3116–3127 (1995).
[CrossRef] [PubMed]

IBM J. Res. Develop.

D. C. Edelstein, G. A. Sai-Halsz, Y.-J. Mii, “VLSI on-chip interconnection performance simulations and measurements,” IBM J. Res. Develop. 39, 383–401 (1995).
[CrossRef]

IEEE Photon. Technol. Lett.

K. H. Calhoun, C. B. Camperi-Ginestet, N. M. Jokerst, “Vertical optical communication through stacked silicon wafers using hybrid monolithic thin film ingaasp emitters and detectors,” IEEE Photon. Technol. Lett. 5, 254–257 (1993).
[CrossRef]

IEEE Trans. Comput.

W. J. Dally, “Performance analysis of k-ary n-cube interconnection networks,” IEEE Trans. Comput. 39, 775–785 (1990).
[CrossRef]

W. J. Dally, “Express (c)ubes: improving the performance of k-ary n-cube interconnection networks,” IEEE Trans. Comput. 40, 1016–1023 (1991).
[CrossRef]

IEEE Trans. Med. Imag.

J. L. Cruz-Rivera, E. V. R. Di Bella, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Parallelized formulation of the maximum likelihood-expectation maximization algorithm for fine-grain message-passing architectures,” IEEE Trans. Med. Imag. 14, 758–762 (1995).
[CrossRef]

IEEE Trans. Parallel Distrib. Syst.

D. S. Wills, H. H. Cat, J. L. Cruz-Rivera, W. S. Lacy, J. M. Baker, J. Eble, A. López-Lagunas, M. Hopper, “High throughput, low memory applications on the pica architecture,” IEEE Trans. Parallel Distrib. Syst. 8, 1055–1067 (1997).
[CrossRef]

IEEE Trans. Parallel Distribut. Syst.

A. Agarwal, “Limits on interconnection network performance,” IEEE Trans. Parallel Distribut. Syst. 2, 398–412 (1991).
[CrossRef]

S. L. Scott, J. R. Goodman, “The impact of pipelined channels on k-ary n-cube networks,” IEEE Trans. Parallel Distribut. Syst. 5, 2–16 (1994).
[CrossRef]

D. Basak, D. K. Panda, “Designing clustered multiprocessor systems under packaging and technological advancements,” IEEE Trans. Parallel Distribut. Syst. 7, 962–978 (1996).
[CrossRef]

J. Lightwave Technol.

R. T. Chen, H. Lu, D. Robinson, M. Wang, G. Savant, T. Jannson, “Guided-wave planar optical interconnects using highly multiplexed polymer waveguide holograms,” J. Lightwave Technol. 10, 888–897 (1992).
[CrossRef]

J. Parallel Distribut. Comput.

S. Abraham, K. Padmanabhan, “Performance of multicomputer networks under pin-out constraints,” J. Parallel Distribut. Comput. 12, 237–248 (1991).
[CrossRef]

Opt. Eng.

M. R. Feldman, C. C. Guest, “Holograms for optical interconnects for very large scale integrated circuits fabricated by electron-beam lithography,” Opt. Eng. 28, 915–921 (1989).
[CrossRef]

S. K. Patra, J. Ma, V. H. Ozguz, S. H. Lee, “Alignment issues in packaging for free-space optical interconnects,” Opt. Eng. 33, 1561–1570 (1994).
[CrossRef]

J. Fan, B. Catanzaro, F. Kiamilev, S. C. Esener, S. H. Lee, “Architecture of an integrated computer-aided design system for optoelectronics,” Opt. Eng. 33, 1571–1580 (1994).
[CrossRef]

Proc. IEEE

R. R. Tummala, “Multichip packaging—a tutorial,” Proc. IEEE 80, 1924–1941 (1992).
[CrossRef]

G. A. Sai-Halsz, “Performance trends in high-end processors,” Proc. IEEE 83, 20–36 (1995).
[CrossRef]

VLSI Design

K. Aoyama, A. A. Chien, “The cost of adaptivity and virtual lanes in a wormhole router,” VLSI Design 2(4), 315–333 (1995).
[CrossRef]

Other

V. J. Sferrino, “Multichip module study,” Tech. Rep. TR9545 (MIT Lincoln Laboratory, Lexington, Mass. 1992).

H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI (Addison-Wesley, Reading, Mass., 1990).

J. W. Goodman, Introduction to Fourier Optics (McGraw-Hill, San Francisco, 1968).

“National technology roadmap for semiconductors,” Tech. Rep., Semiconductor Industry Association, San José, Calif. (1994).

M. Raksapatcharawong, T. M. Pinkston, “An optical interconnect model for k-ary n-cube wormhole networks,” in Proceedings of the Tenth International Parallel Processing Symposium (IEEE Computer Society, Los Alamitos, Calif., 1996), pp. 666–672.

J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Architectural desin issues for optoelectronic k-ary n-cube interconnection networks,” presented at the 1995 Optical Society of America Annual Meeting, Portland, Oregon, 10–15 September 1995.

J. L. Cruz-Rivera, W. S. Lacy, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Performance modeling of optical interconnection technologies for massively parallel processing systems,” in Proceedings of the Third International Workshop on Massively Parallel Processing Using Optical Interconnections, A. Gottlieb, Y. Li, E. Schenfeld, eds. (IEEE Computer Society, Los Alamitos Calif., 1996), pp. 264–275.
[CrossRef]

J. L. Cruz-Rivera, D. S. Wills, T. K. Gaylord, E. N. Glytsis, “Modeling the technology impact on the design of a two-level multicomputer interconnection network,” in Proceedings of the 1996 International Conference on Computer Design (IEEE Computer Society, Los Alamitos Calif., 1996), pp. 165–169.

W. S. Lacy, J. L. Cruz-Rivera, D. S. Wills, “The offset cube: a three-dimensional multicomputer network topology using through-wafer optics,” IEEE Trans. Parallel Distribut. Syst. (to be published).

R. A. Soref, F. Namavar, E. Cortesi, L. Friedman, R. Lareau, “Vertical 3-d integration of silicon waveguides in Si–SiO2–Si–SiO2–Si structure,” in Microelectronic Interconnects and Packages: Optical and Electrical Technologies, G. Arjavalingam, J. Pazaris, eds., Proc. SPIE1389, 408–421 (1990).
[CrossRef]

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Figures (10)

Fig. 1
Fig. 1

Diffractive–reflective optoelectronic MCM.

Fig. 2
Fig. 2

(a) Chip and (b) MCM floor plans used in the technological model. The silicon area of each chip is shared by the C processing nodes that comprise a cluster, the level-1 router and associated interface circuitry, and a pad frame for areally distributed chip pins (flip-chip bonding).

Fig. 3
Fig. 3

Physical lengths associated with (a) processors and (b) chips.

Fig. 4
Fig. 4

Physical representation of (a) collimated-beam and (b) focused-beam configurations.

Fig. 5
Fig. 5

Distances involved in the determination of the level-1 network cycle time.

Fig. 6
Fig. 6

(a) Minimum total average no-load latency for minimum-pitch (f w = 1) and wide, non-minimum-pitch (f w = 6) wires across the cluster size for the wire-based baseline configuration. (b) Optimal level-0 and level-1 network dimensionalities for the baseline MCM technology that uses minimum-pitch (f w = 1) on-chip wires.

Fig. 7
Fig. 7

Minimum total average no-load latency and level-0 and level-1 latency components across cluster size for the baseline MCM technology with f w = 1.

Fig. 8
Fig. 8

Minimum total average no-load latency across various technological generations indexed by VLSI feature size. The wide-wire curve corresponds to the latency values obtained by a search of the design space across f w factors; the minimum pitch and the linear latency scaling curves are presented for reference.

Fig. 9
Fig. 9

Minimum total average no-load latency (line graph) and optimal level-0 and level-1 (electrical and optical) network dimensionalities (bar graphs) across cluster size for the collimated-beam, diffractive–reflective baseline configuration with f d = 1. The latency curve for the baseline wire-based case is shown for reference.

Fig. 10
Fig. 10

Minimum total average no-load latency (line graph) and optimal level-0 and level-1 (electrical and optical) network dimensionalities (bar graphs) across cluster size for the focused-beam, diffractive–reflective baseline configuration with f d = 1. The latency curve for the baseline wire-based case is shown for reference.

Tables (6)

Tables Icon

Table 1 Technological Parameters for the Baseline Wire-Based MCM Configuration

Tables Icon

Table 2 Assumed Parameters across VLSI and MCM Technological Generations

Tables Icon

Table 3 Optimal System Implementation Results across DOE Clearance Factors fd for the Baseline Collimated-Beam, Diffractive–Reflective Optoelectronic Configuration

Tables Icon

Table 4 Optimal System Implementation Results across Technological Generations for the Baseline Collimated-Beam Configuration

Tables Icon

Table 5 Optimal System Implementation Results across DOE Pitch Pdoe for the Baseline Focused-Beam Configuration

Tables Icon

Table 6 Optimal System Implementation Results across Technological Generations for the Baseline Focused-Beam Configuration

Equations (32)

Equations on this page are rendered with MathJax. Learn more.

WLA 0 = e w n w p w A C ,
T w 0 = 0.7 R tr + 0.4 R int l C int l + t fc 2.5 R tr C tr R int C int 1 / 2 l + t fc 0.7 fR tr C tr   ln C int l + C tr C tr + 0.4 R int C int l 2 + 0.7 R int C tr l + t fc minimum - sized   drivers optimal   repeaters cascaded   drivers ,
NPA 1 o = f o f s f p D c 2 A d o ,
NDA 1 o = f s f p D c 2 P doe 2 ,
T w 1 o = T oe + T fo + T eo ,
WLA 1 e = E w N w P w D m 2 ,
NPA 1 e = 1 - f o f i f s f p D c 2 P p 2 ,
T w 1 e = 15 S - 1 R tr C tr + 2 Z 0 C p + R INT C INT l 2 + t fm ,
T T = T L 0 p + T L 1 + 2 T L 0 1 - p ,
T L 0 = T c 0 H 0 T h 0 c + T su 0 c + P 0 - 1 ,
T L 1 = T L 1 e + T L 1 o .
T L 1 e = T c 1 e 2 H 1 e T su 1 ce + T h 1 ce + L W 1 e - 1 ,
T L 1 o = T c 1 o 2 H 1 o T su 1 co + T h 1 co + L W 1 o - 1 ,
γ oe = n 1 e W 1 e T c 1 e + n 1 o W 1 o T c 1 o C 1 - p 2 H 1 e + H 1 o L ,
W 0 = min W 0 l ,   W 0 p = min WLA 0 WLR 0 ,   W 0 p ,
W 0 l = e w n w A C p w / n 0 Cl avg 0 ;
W 1 e = min NPA 1 e NPR 1 e ,   WLA 1 e WLR 1 e | n 1 e ,
l avg = l 2 d k - 1 k 1 + k + + k n / 2 - 1 2 n
= 2 l 2 d n k - 1 k k n / 2 - 1 k - 1
= 2 l 2 d kn k n / 2 - 1 ,
W 1 o = min NPA 1 o NPR 1 o ,   NDA 1 o NDR 1 o ,
A doe = π 1.2 λ l 2 D doe tx 2 cos 4   θ   tan 2   θ .
A doe = 2.4 π λ l = 4.25 λ l ,
D doe = A doe 1 / 2 = 4.25 λ l 1 / 2 .
P doe = f d D doe = f d 4.25 λ l max 1 1 / 2 .
T c 0 = T dt 0 + T w 0 | l max 0 ,
T c 1 = max T dt 1 + T w 1 | l max 1 ,   T dt 1 + T cx ,
l max = l 1 d 1 / 4 l 2 d k n / 2 l 2 d k n / 2 - 1 n = 1 k = 2 ,   n 1 k > 2 ,   n 1 .
T c 1 e = max T dt 1 + T cx ,   T dt 1 + T w 1 e | n 1 e ,
T c 1 o = max T dt 1 + T cx ,   T dt 1 + T w 1 o ,
γ rel = γ oe γ ,
T T rel = T T T T oe ,

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