Abstract

There is considerable interest in the development of optical interconnects for multichip modules (MCM’s) to improve their performance. For effective utilization of the optical and electronic technologies, a methodology for partitioning the system is required. The key question to be answered is which technology should be used for each interconnect in a given netlist: optical or electronic. We introduce the computer-aided design approach for partitioning optoelectronic systems into optoelectronic MCM’s. We first discuss the design trade-off issues in an optoelectronic system design, including speed, power dissipation, area, and diffraction limits for free-space optics. We then define a formulation for optoelectronic MCM partitioning and describe new algorithms for optimizing this partitioning based on the minimization of the power dissipation. The models for the algorithms are discussed in detail, and an example of a multistage interconnect network is given. Different results, with the number and size of chips being variable, are presented in which improvement for the system packaging has been observed when the partitioning algorithms are applied.

© 1995 Optical Society of America

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References

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  1. J. W. Goodman, F. J. Leonberger, S. -C. Kung, R. A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE 72, 850–866 (1984).
    [CrossRef]
  2. M. R. Feldman, S. C. Esener, C. C. Guest, S. H. Lee, “Comparison between optical and electrical interconnects based on power and speed considerations,” Appl. Opt. 27, 1742–1751 (1988).
    [CrossRef] [PubMed]
  3. A. V. Krishnamoorthy, P. Marchand, F. Kiamilev, S. C. Esener, “Grain-size considerations for optoelectronic multistage interconnection networks,” Appl. Opt. 31, 5480–5507 (1992).
    [CrossRef] [PubMed]
  4. T. J. Cloonan, “Comparative study of optical and electronic interconnection technologies for large asynchronous transfer mode packet switching application,” Opt. Eng. 33, 1512–1523 (1994).
    [CrossRef]
  5. H. M. Ozaktas, J. W. Goodman, “Elements of a hybrid interconnection theory,” Appl. Opt. 33, 2968–2987 (1994).
    [CrossRef] [PubMed]
  6. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI (Addison-Wesley, Reading, Mass, 1990), p. 55.
  7. C.-S. Li, H. S. Stone, Y. Kwark, C. M. Olsen, “Fully differential optical interconnections for high-speed digital systems,” IEEE Trans. VLSI Sys. 1, 151–163 (1993).
    [CrossRef]
  8. B. Mansoorian, V. Ozguz, S. Esener, “Diode-biased AC-coupled ECL-to-CMOS interface circuit,” IEEE J. Solid-State Circuits 28, 397–399 (1993).
    [CrossRef]
  9. P. J. W. Lim, A. Y. C. Tzeng, H. L. Chuange, S. A. St. Onge, “Monolithic photodetector/CMOS preamplifier for 531 Mb/s optical data link applications,” in Proceedings of International Solid-State Circuits Conference 93 (Broadband Data, San Francisco, Calif., 1993), pp. 70–71.
  10. D. Zaleta, J. Fan, B. C. Kress, S. H. Lee, C. K. Cheng, “Optimum placement for optoelectronic multichip modules and the synthesis of diffractive optics for MCM interconnects,” Appl. Opt. 33, 1444–1456 (1994).
    [CrossRef] [PubMed]
  11. S. H. Lee, “Diffractive optics and computer generated holograms for optical interconnects,” in Diffractive and Miniaturized Optics, S. H. Lee, ed., Vol. CR-49 of SPIE Critical Reviews Series (Society of Photo-Optical Instrumentation Engineers, Bellingham, Wash., 1993).
  12. F. Sauer, J. Jahns, C. R. Nijander, A. Y. Feldblum, W. P. Townsend, “Refractive-diffractive micro-optics for permutation interconnects,” Opt. Eng. 33, 1550–1560 (1994).
    [CrossRef]
  13. M. Shih, E. S. Kuh, “Quadratic boolean programming for performance-driven system partitioning,” in Proceedings of the 30th ACM/IEEE Design Automation Conference (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 761–765.
  14. R. E. Burkard, T. Bonniger, “A heuristic for quadratic boolean programs with applications to quadratic assignment problems,” Eur. J. Oper. Res. 13, 372–386 (1983).
    [CrossRef]
  15. E. L. Lawler, Combinatorial Optimization: Networks and Matroids (Holt, Rinehart & Winston, New York, 1976), Sect. 5.7.
  16. J. Fan, D. Zaleta, C. K. Cheng, S. H. Lee, “Physical layout for computer-generated holograms for optoelectronic multichip modules,” in Proceedings of the IEEE MCM Conference 93 (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 198–203.
    [CrossRef]
  17. F. T. Leighton, B. M. Maggs, “Fast algorithms for routing around faults in multibutterflies and randomly wired splitter networks,” IEEE Trans. Comput. 41, 578–587 (1992).
    [CrossRef]

1994 (4)

T. J. Cloonan, “Comparative study of optical and electronic interconnection technologies for large asynchronous transfer mode packet switching application,” Opt. Eng. 33, 1512–1523 (1994).
[CrossRef]

F. Sauer, J. Jahns, C. R. Nijander, A. Y. Feldblum, W. P. Townsend, “Refractive-diffractive micro-optics for permutation interconnects,” Opt. Eng. 33, 1550–1560 (1994).
[CrossRef]

D. Zaleta, J. Fan, B. C. Kress, S. H. Lee, C. K. Cheng, “Optimum placement for optoelectronic multichip modules and the synthesis of diffractive optics for MCM interconnects,” Appl. Opt. 33, 1444–1456 (1994).
[CrossRef] [PubMed]

H. M. Ozaktas, J. W. Goodman, “Elements of a hybrid interconnection theory,” Appl. Opt. 33, 2968–2987 (1994).
[CrossRef] [PubMed]

1993 (2)

C.-S. Li, H. S. Stone, Y. Kwark, C. M. Olsen, “Fully differential optical interconnections for high-speed digital systems,” IEEE Trans. VLSI Sys. 1, 151–163 (1993).
[CrossRef]

B. Mansoorian, V. Ozguz, S. Esener, “Diode-biased AC-coupled ECL-to-CMOS interface circuit,” IEEE J. Solid-State Circuits 28, 397–399 (1993).
[CrossRef]

1992 (2)

F. T. Leighton, B. M. Maggs, “Fast algorithms for routing around faults in multibutterflies and randomly wired splitter networks,” IEEE Trans. Comput. 41, 578–587 (1992).
[CrossRef]

A. V. Krishnamoorthy, P. Marchand, F. Kiamilev, S. C. Esener, “Grain-size considerations for optoelectronic multistage interconnection networks,” Appl. Opt. 31, 5480–5507 (1992).
[CrossRef] [PubMed]

1988 (1)

1984 (1)

J. W. Goodman, F. J. Leonberger, S. -C. Kung, R. A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE 72, 850–866 (1984).
[CrossRef]

1983 (1)

R. E. Burkard, T. Bonniger, “A heuristic for quadratic boolean programs with applications to quadratic assignment problems,” Eur. J. Oper. Res. 13, 372–386 (1983).
[CrossRef]

Athale, R. A.

J. W. Goodman, F. J. Leonberger, S. -C. Kung, R. A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE 72, 850–866 (1984).
[CrossRef]

Bakoglu, H. B.

H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI (Addison-Wesley, Reading, Mass, 1990), p. 55.

Bonniger, T.

R. E. Burkard, T. Bonniger, “A heuristic for quadratic boolean programs with applications to quadratic assignment problems,” Eur. J. Oper. Res. 13, 372–386 (1983).
[CrossRef]

Burkard, R. E.

R. E. Burkard, T. Bonniger, “A heuristic for quadratic boolean programs with applications to quadratic assignment problems,” Eur. J. Oper. Res. 13, 372–386 (1983).
[CrossRef]

Cheng, C. K.

D. Zaleta, J. Fan, B. C. Kress, S. H. Lee, C. K. Cheng, “Optimum placement for optoelectronic multichip modules and the synthesis of diffractive optics for MCM interconnects,” Appl. Opt. 33, 1444–1456 (1994).
[CrossRef] [PubMed]

J. Fan, D. Zaleta, C. K. Cheng, S. H. Lee, “Physical layout for computer-generated holograms for optoelectronic multichip modules,” in Proceedings of the IEEE MCM Conference 93 (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 198–203.
[CrossRef]

Chuange, H. L.

P. J. W. Lim, A. Y. C. Tzeng, H. L. Chuange, S. A. St. Onge, “Monolithic photodetector/CMOS preamplifier for 531 Mb/s optical data link applications,” in Proceedings of International Solid-State Circuits Conference 93 (Broadband Data, San Francisco, Calif., 1993), pp. 70–71.

Cloonan, T. J.

T. J. Cloonan, “Comparative study of optical and electronic interconnection technologies for large asynchronous transfer mode packet switching application,” Opt. Eng. 33, 1512–1523 (1994).
[CrossRef]

Esener, S.

B. Mansoorian, V. Ozguz, S. Esener, “Diode-biased AC-coupled ECL-to-CMOS interface circuit,” IEEE J. Solid-State Circuits 28, 397–399 (1993).
[CrossRef]

Esener, S. C.

Fan, J.

D. Zaleta, J. Fan, B. C. Kress, S. H. Lee, C. K. Cheng, “Optimum placement for optoelectronic multichip modules and the synthesis of diffractive optics for MCM interconnects,” Appl. Opt. 33, 1444–1456 (1994).
[CrossRef] [PubMed]

J. Fan, D. Zaleta, C. K. Cheng, S. H. Lee, “Physical layout for computer-generated holograms for optoelectronic multichip modules,” in Proceedings of the IEEE MCM Conference 93 (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 198–203.
[CrossRef]

Feldblum, A. Y.

F. Sauer, J. Jahns, C. R. Nijander, A. Y. Feldblum, W. P. Townsend, “Refractive-diffractive micro-optics for permutation interconnects,” Opt. Eng. 33, 1550–1560 (1994).
[CrossRef]

Feldman, M. R.

Goodman, J. W.

H. M. Ozaktas, J. W. Goodman, “Elements of a hybrid interconnection theory,” Appl. Opt. 33, 2968–2987 (1994).
[CrossRef] [PubMed]

J. W. Goodman, F. J. Leonberger, S. -C. Kung, R. A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE 72, 850–866 (1984).
[CrossRef]

Guest, C. C.

Jahns, J.

F. Sauer, J. Jahns, C. R. Nijander, A. Y. Feldblum, W. P. Townsend, “Refractive-diffractive micro-optics for permutation interconnects,” Opt. Eng. 33, 1550–1560 (1994).
[CrossRef]

Kiamilev, F.

Kress, B. C.

Krishnamoorthy, A. V.

Kuh, E. S.

M. Shih, E. S. Kuh, “Quadratic boolean programming for performance-driven system partitioning,” in Proceedings of the 30th ACM/IEEE Design Automation Conference (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 761–765.

Kung, S. -C.

J. W. Goodman, F. J. Leonberger, S. -C. Kung, R. A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE 72, 850–866 (1984).
[CrossRef]

Kwark, Y.

C.-S. Li, H. S. Stone, Y. Kwark, C. M. Olsen, “Fully differential optical interconnections for high-speed digital systems,” IEEE Trans. VLSI Sys. 1, 151–163 (1993).
[CrossRef]

Lawler, E. L.

E. L. Lawler, Combinatorial Optimization: Networks and Matroids (Holt, Rinehart & Winston, New York, 1976), Sect. 5.7.

Lee, S. H.

D. Zaleta, J. Fan, B. C. Kress, S. H. Lee, C. K. Cheng, “Optimum placement for optoelectronic multichip modules and the synthesis of diffractive optics for MCM interconnects,” Appl. Opt. 33, 1444–1456 (1994).
[CrossRef] [PubMed]

M. R. Feldman, S. C. Esener, C. C. Guest, S. H. Lee, “Comparison between optical and electrical interconnects based on power and speed considerations,” Appl. Opt. 27, 1742–1751 (1988).
[CrossRef] [PubMed]

J. Fan, D. Zaleta, C. K. Cheng, S. H. Lee, “Physical layout for computer-generated holograms for optoelectronic multichip modules,” in Proceedings of the IEEE MCM Conference 93 (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 198–203.
[CrossRef]

S. H. Lee, “Diffractive optics and computer generated holograms for optical interconnects,” in Diffractive and Miniaturized Optics, S. H. Lee, ed., Vol. CR-49 of SPIE Critical Reviews Series (Society of Photo-Optical Instrumentation Engineers, Bellingham, Wash., 1993).

Leighton, F. T.

F. T. Leighton, B. M. Maggs, “Fast algorithms for routing around faults in multibutterflies and randomly wired splitter networks,” IEEE Trans. Comput. 41, 578–587 (1992).
[CrossRef]

Leonberger, F. J.

J. W. Goodman, F. J. Leonberger, S. -C. Kung, R. A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE 72, 850–866 (1984).
[CrossRef]

Li, C.-S.

C.-S. Li, H. S. Stone, Y. Kwark, C. M. Olsen, “Fully differential optical interconnections for high-speed digital systems,” IEEE Trans. VLSI Sys. 1, 151–163 (1993).
[CrossRef]

Lim, P. J. W.

P. J. W. Lim, A. Y. C. Tzeng, H. L. Chuange, S. A. St. Onge, “Monolithic photodetector/CMOS preamplifier for 531 Mb/s optical data link applications,” in Proceedings of International Solid-State Circuits Conference 93 (Broadband Data, San Francisco, Calif., 1993), pp. 70–71.

Maggs, B. M.

F. T. Leighton, B. M. Maggs, “Fast algorithms for routing around faults in multibutterflies and randomly wired splitter networks,” IEEE Trans. Comput. 41, 578–587 (1992).
[CrossRef]

Mansoorian, B.

B. Mansoorian, V. Ozguz, S. Esener, “Diode-biased AC-coupled ECL-to-CMOS interface circuit,” IEEE J. Solid-State Circuits 28, 397–399 (1993).
[CrossRef]

Marchand, P.

Nijander, C. R.

F. Sauer, J. Jahns, C. R. Nijander, A. Y. Feldblum, W. P. Townsend, “Refractive-diffractive micro-optics for permutation interconnects,” Opt. Eng. 33, 1550–1560 (1994).
[CrossRef]

Olsen, C. M.

C.-S. Li, H. S. Stone, Y. Kwark, C. M. Olsen, “Fully differential optical interconnections for high-speed digital systems,” IEEE Trans. VLSI Sys. 1, 151–163 (1993).
[CrossRef]

Ozaktas, H. M.

Ozguz, V.

B. Mansoorian, V. Ozguz, S. Esener, “Diode-biased AC-coupled ECL-to-CMOS interface circuit,” IEEE J. Solid-State Circuits 28, 397–399 (1993).
[CrossRef]

Sauer, F.

F. Sauer, J. Jahns, C. R. Nijander, A. Y. Feldblum, W. P. Townsend, “Refractive-diffractive micro-optics for permutation interconnects,” Opt. Eng. 33, 1550–1560 (1994).
[CrossRef]

Shih, M.

M. Shih, E. S. Kuh, “Quadratic boolean programming for performance-driven system partitioning,” in Proceedings of the 30th ACM/IEEE Design Automation Conference (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 761–765.

St. Onge, S. A.

P. J. W. Lim, A. Y. C. Tzeng, H. L. Chuange, S. A. St. Onge, “Monolithic photodetector/CMOS preamplifier for 531 Mb/s optical data link applications,” in Proceedings of International Solid-State Circuits Conference 93 (Broadband Data, San Francisco, Calif., 1993), pp. 70–71.

Stone, H. S.

C.-S. Li, H. S. Stone, Y. Kwark, C. M. Olsen, “Fully differential optical interconnections for high-speed digital systems,” IEEE Trans. VLSI Sys. 1, 151–163 (1993).
[CrossRef]

Townsend, W. P.

F. Sauer, J. Jahns, C. R. Nijander, A. Y. Feldblum, W. P. Townsend, “Refractive-diffractive micro-optics for permutation interconnects,” Opt. Eng. 33, 1550–1560 (1994).
[CrossRef]

Tzeng, A. Y. C.

P. J. W. Lim, A. Y. C. Tzeng, H. L. Chuange, S. A. St. Onge, “Monolithic photodetector/CMOS preamplifier for 531 Mb/s optical data link applications,” in Proceedings of International Solid-State Circuits Conference 93 (Broadband Data, San Francisco, Calif., 1993), pp. 70–71.

Zaleta, D.

D. Zaleta, J. Fan, B. C. Kress, S. H. Lee, C. K. Cheng, “Optimum placement for optoelectronic multichip modules and the synthesis of diffractive optics for MCM interconnects,” Appl. Opt. 33, 1444–1456 (1994).
[CrossRef] [PubMed]

J. Fan, D. Zaleta, C. K. Cheng, S. H. Lee, “Physical layout for computer-generated holograms for optoelectronic multichip modules,” in Proceedings of the IEEE MCM Conference 93 (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 198–203.
[CrossRef]

Appl. Opt. (4)

Eur. J. Oper. Res. (1)

R. E. Burkard, T. Bonniger, “A heuristic for quadratic boolean programs with applications to quadratic assignment problems,” Eur. J. Oper. Res. 13, 372–386 (1983).
[CrossRef]

IEEE J. Solid-State Circuits (1)

B. Mansoorian, V. Ozguz, S. Esener, “Diode-biased AC-coupled ECL-to-CMOS interface circuit,” IEEE J. Solid-State Circuits 28, 397–399 (1993).
[CrossRef]

IEEE Trans. Comput. (1)

F. T. Leighton, B. M. Maggs, “Fast algorithms for routing around faults in multibutterflies and randomly wired splitter networks,” IEEE Trans. Comput. 41, 578–587 (1992).
[CrossRef]

IEEE Trans. VLSI Sys. (1)

C.-S. Li, H. S. Stone, Y. Kwark, C. M. Olsen, “Fully differential optical interconnections for high-speed digital systems,” IEEE Trans. VLSI Sys. 1, 151–163 (1993).
[CrossRef]

Opt. Eng. (2)

T. J. Cloonan, “Comparative study of optical and electronic interconnection technologies for large asynchronous transfer mode packet switching application,” Opt. Eng. 33, 1512–1523 (1994).
[CrossRef]

F. Sauer, J. Jahns, C. R. Nijander, A. Y. Feldblum, W. P. Townsend, “Refractive-diffractive micro-optics for permutation interconnects,” Opt. Eng. 33, 1550–1560 (1994).
[CrossRef]

Proc. IEEE (1)

J. W. Goodman, F. J. Leonberger, S. -C. Kung, R. A. Athale, “Optical interconnections for VLSI systems,” Proc. IEEE 72, 850–866 (1984).
[CrossRef]

Other (6)

H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI (Addison-Wesley, Reading, Mass, 1990), p. 55.

M. Shih, E. S. Kuh, “Quadratic boolean programming for performance-driven system partitioning,” in Proceedings of the 30th ACM/IEEE Design Automation Conference (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 761–765.

P. J. W. Lim, A. Y. C. Tzeng, H. L. Chuange, S. A. St. Onge, “Monolithic photodetector/CMOS preamplifier for 531 Mb/s optical data link applications,” in Proceedings of International Solid-State Circuits Conference 93 (Broadband Data, San Francisco, Calif., 1993), pp. 70–71.

S. H. Lee, “Diffractive optics and computer generated holograms for optical interconnects,” in Diffractive and Miniaturized Optics, S. H. Lee, ed., Vol. CR-49 of SPIE Critical Reviews Series (Society of Photo-Optical Instrumentation Engineers, Bellingham, Wash., 1993).

E. L. Lawler, Combinatorial Optimization: Networks and Matroids (Holt, Rinehart & Winston, New York, 1976), Sect. 5.7.

J. Fan, D. Zaleta, C. K. Cheng, S. H. Lee, “Physical layout for computer-generated holograms for optoelectronic multichip modules,” in Proceedings of the IEEE MCM Conference 93 (IEEE Computer Society, Los Alamitos, Calif., 1993), pp. 198–203.
[CrossRef]

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Figures (9)

Fig. 1
Fig. 1

Schematic of a physical model of an OE MCM package in reflective configuration (only a few of the many actual interconnects are shown); CGH, computer-generated hologram.

Fig. 2
Fig. 2

Cross section of an OE MCM.

Fig. 3
Fig. 3

Top view of an OE MCM with 20 chips. The interconnections between chips are optical and those inside chips are electronic.

Fig. 4
Fig. 4

Total weight algorithm (in Subsection 3.B.1) convergence for several different chip counts. Vertical axis is the number of optical interconnects over total interconnects.

Fig. 5
Fig. 5

Comparison of the power dissipation of the interconnects between random partitioning and algorithm partitioning. Over 50% improvement can be achieved by application of the algorithm.

Fig. 6
Fig. 6

Heat generated by the 4 × 5 OE MCM as a function of the maximum optical interconnect distance allowed.

Fig. 7
Fig. 7

Worst-case heat dissipation for any chip after the algorithm in Subsection 3.B.2 is applied for the 4 × 5 OE MCM, as a function of the maximum optical interconnect distance allowed. Nmax is the number of optical interconnects on the worst-case chip.

Fig. 8
Fig. 8

Straightforward partitioning of a twin-butterfly interconnection network into a 4 × 5 OE MCM (left). The numbers of optical interconnects on each chip are listed (right). The pw[i] is the number of optical interconnects for the ith chip. The netlist is in Ref. 16, with a total of 448 SE’s. The connection lines are drawn on the hottest chip in the system.

Fig. 9
Fig. 9

Algorithm partitioning (in Subsection 3.B.2) of a twin-butterfly interconnection network into a 4 × 5 OE MCM (left). The numbers of optical interconnects on each chip are listed (right). The result for the maximum power dissipation on a single chip is ~50% better than the result in random partitioning. The connection lines are drawn on the hottest chip in the system.

Tables (3)

Tables Icon

Table 1 Performance Data for CMOS Detectors and Their Driver Designs

Tables Icon

Table 2 Summary of Heat Dissipated per Optical Link by Different Combinations of Optical Transmitter and Receiver Technologies

Tables Icon

Table 3 Technology Variables for Computer-Generated Hologram Fabrication

Equations (19)

Equations on this page are rendered with MathJax. Learn more.

S opt < π λ w i w o .
L opt < π λ D t D r 16 sin ( θ ) ,
P total = P p + P net .
P total = P p + N o ( P o P e ) + P e N net .
V i = V , V i V j = , i j
C ( v ) = Src ( v ) Des ( v ) .
s ( v ) = size of v , p ( a ) = power required by a V E , t ( c ) = time required for c E .
Int E ( V i ) = v V i { ( v , v ) E and v Int i ( v ) } , Ext E ( V i ) = v V i { ( v , v ) E and v Ext i ( v ) } .
MID ( V i ) = max v V i { dist ( v , v ) | v Ext i ( v ) } ,
J = i Int E ( V i ) , Q = i Ext E ( V i ) .
v V i s ( v ) s , i .
| V i | s / s ( v ) = N 3 ,
t ( e ) t i , e Int i E ( V i ) , t ( e ) t e , e Ext i E ( V i ) .
MID ( V i ) D _ LIMIT , i .
a V p ( a ) + a E p ( a ) p .
min a E p ( a ) min { a J p ( a ) + a Q p ( a ) } .
min a Q p ( a ) min | i Ext E ( V i ) | .
a V i p ( a ) + a Ext E ( V i ) p ( a ) p , i .
min max i | Ext E ( V i ) | .

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