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Butterfly interconnection network: design of multiplier, flip-flop, and shift register

Khan M. Iftekharuddin and Mohammad A. Karim

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Abstract

A 2 × 2 bit multiplier is designed by the use of a butterfly interconnection network. The butterfly topology is also used to design a sequential flip-flop and a multibit parallel-in parallel-out shift register.

© 1994 Optical Society of America

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