For industrial use, adaptive resonance theory (ART) neural networks have the potential of becoming an important component in a variety of commercial and military systems. Efficient software emulations of these networks are adequate in many of today’s low-end applications such as information retrieval or group technology. But for larger applications, special-purpose hardware is required to achieve the expected performance requirements. Direct electronic implementation of this network model has proven difficult to scale to large-input dimensionality owing to the high degree of interconnectivity between layers. Here, a new hardware implementation design of ART1 is proposed that handles input dimensions of practical size. It efficiently combines the advantages of optical and electronic devices to produce a stand-alone ART1 processor. Parallel computations are relegated to free-space optics, while serial operations are performed in VLSI electronics. One possible physical realization of this architecture is proposed. No hardware has as yet been built.
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These operations can be partitioned naturally between electronic and optical implementations, as indicated by the check marks. The last column gives an approximate percentage of execution time in the ART1 algorithm.
Representation of information as a light intensity or transmissivity.
Assuming that Nbit = 1024 and nc = 100.
Table 2
Truth Table Showing the Copying Operation Required to Generate a New Cluster Templatea
Bk is the output of the kth emitter on the SO array, and is ON when the kth template is to be created.
SI array mode = 1, inverted input pattern.
Threshold for toggle of SSLM pixel flip-flip ≅ 2.5 and ∑n = Bk + Īn + Tkninitial.
Values for the only condition in which a change of state of a template pixel occurs.
Table 3
Truth Table Showing the Operation Required to Update a Cluster Templatea
Bk is the output of the kth emitter on the SO array, and is ON when the kth template is to be updated.
SI array mode = 1, inverted input pattern.
Threshold for toggle of SSLM pixel flip-flip ≅ 2.5 and ∑n = Bk + Īn + Tkninitial.
Values for the only condition in which a change of state of a template pixel occurs.
Table 4
Mapping of the ART1 Algorithm Into Processing Steps of the Optical Processor
Step
SO Array
SI Array
SSLM
SEARCH AND MATCH operation
1.
Output mode = 0 to SI array
Shift in input, mode = 0
Subthreshold
2.
Integrate detectors
Emitters ON
3.
Store input norm
4.
Normalize dot products with template norms
5.
If no active clusters, then GOTO COPY
Mode changing
Superthreshold, pixel toggling
6.
Winner-take-all finds max index
7.
If FAIL first inequality, then GOTO COPY
Mode changing
Superthreshold, pixel toggling
8.
If FAIL second inequality, proceed as follows:
(1) Decrement number of active clusters
(2) If none left, then GOTO COPY
Mode changing
Superthreshold, pixel toggling
(3) Otherwise, inhibit winning cluster and GOTO step 5
9.
Resonance, output cluster
10.
GOTO UPDATE
Mode changing
Superthreshold, pixel toggling
11.
GOTO step 1
COPY operation
a.
Output mode = 1 to SI array
Invert input, mode = 1
Subthreshold
b.
Backemitter ON for next available cluster index
Emitters ON
Pixels toggle
c.
Backemitter OFF
d.
Output mode = 2 to SI array
All ones, mode = 2
Subthreshold
e.
Integrate detectors
Emitters ON
f.
Store template norms
g.
GOTO step 1
UPDATE operation
a.
Output mode = 1 to SI array
Invert input, mode = 1
Subthreshold
b.
Backemitter ON for winning cluster index
Emitters ON
Pixels toggle
c.
Backemitter OFF
d.
Output mode = 2 to SI array
All 1’s, mode = 2
Subthreshold
e.
Integrate detectors
Emitters ON
f.
Store template norms
g.
GOTO step 1
Tables (4)
Table 1
List of Principal Computational Operations Required to Performing the ART1 Algorithma
These operations can be partitioned naturally between electronic and optical implementations, as indicated by the check marks. The last column gives an approximate percentage of execution time in the ART1 algorithm.
Representation of information as a light intensity or transmissivity.
Assuming that Nbit = 1024 and nc = 100.
Table 2
Truth Table Showing the Copying Operation Required to Generate a New Cluster Templatea
Bk is the output of the kth emitter on the SO array, and is ON when the kth template is to be created.
SI array mode = 1, inverted input pattern.
Threshold for toggle of SSLM pixel flip-flip ≅ 2.5 and ∑n = Bk + Īn + Tkninitial.
Values for the only condition in which a change of state of a template pixel occurs.
Table 3
Truth Table Showing the Operation Required to Update a Cluster Templatea
Bk is the output of the kth emitter on the SO array, and is ON when the kth template is to be updated.
SI array mode = 1, inverted input pattern.
Threshold for toggle of SSLM pixel flip-flip ≅ 2.5 and ∑n = Bk + Īn + Tkninitial.
Values for the only condition in which a change of state of a template pixel occurs.
Table 4
Mapping of the ART1 Algorithm Into Processing Steps of the Optical Processor
Step
SO Array
SI Array
SSLM
SEARCH AND MATCH operation
1.
Output mode = 0 to SI array
Shift in input, mode = 0
Subthreshold
2.
Integrate detectors
Emitters ON
3.
Store input norm
4.
Normalize dot products with template norms
5.
If no active clusters, then GOTO COPY
Mode changing
Superthreshold, pixel toggling
6.
Winner-take-all finds max index
7.
If FAIL first inequality, then GOTO COPY
Mode changing
Superthreshold, pixel toggling
8.
If FAIL second inequality, proceed as follows:
(1) Decrement number of active clusters
(2) If none left, then GOTO COPY
Mode changing
Superthreshold, pixel toggling
(3) Otherwise, inhibit winning cluster and GOTO step 5
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