Abstract

This paper investigates, at the system level, the performance–cost trade-off between optical and electronic interconnects in an optoelectronic interconnection network. The specific system considered is a packet-switched, free-space optoelectronic shuffle-exchange multistage interconnection network (MIN). System bandwidth is used as the performance measure, while system area, system power, and system volume constitute the cost measures. A detailed design and analysis of a two-dimensional (2-D) optoelectronic shuffle-exchange routing network with variable grain size K is presented. The architecture permits the conventional 2 × 2 switches or grains to be generalized to larger K × K grain sizes by replacing optical interconnects with electronic wires without affecting the functionality of the system. Thus the system consists of logK N optoelectronic stages interconnected with free-space K-shuffles. When K = N, the MIN consists of a single electronic stage with optical input–output. The system design uses an efficient 2-D VLSI layout and a single diffractive optical element between stages to provide the 2-D K-shuffle interconnection. Results indicate that there is an optimum range of grain sizes that provides the best performance per cost. For the specific VLSI/GaAs multiple quantum well technology and system architecture considered, grain sizes larger than 256 × 256 result in a reduced performance, while grain sizes smaller than 16 × 16 have a high cost. For a network with 4096 channels, the useful range of grain sizes corresponds to approximately 250–400 electronic transistors per optical input–output channel. The effect of varying certain technology parameters such as the number of hologram phase levels, the modulator driving voltage, the minimum detectable power, and VLSI minimum feature size on the optimum grain-size system is studied. For instance, results show that using four phase levels for the interconnection hologram is a good compromise for the cost functions mentioned above. As VLSI minimum feature sizes decrease, the optimum grain size increases, whereas, if optical interconnect performance in terms of the detector power or modulator driving voltage requirements improves, the optimum grain size may be reduced. Finally, several architectural modifications to the system, such as K × K contention-free switches and sorting networks, are investigated and optimized for grain size. Results indicate that system bandwidth can be increased, but at the price of reduced performance/cost. The optoelectronic MIN architectures considered thus provide a broad range of performance/cost alternatives and offer a superior performance over purely electronic MIN’s.

© 1992 Optical Society of America

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  1. A. L. Decegama, Parallel Processing Architectures and VLSI Hardware (Prentice-Hall, Englewood Cliffs, N.J., 1989), Vol. 1, Chap. 1.
  2. H. J. Siegel, Interconnection Networks for Large-Scale Parallel Processing, 2nd ed. (McGraw-Hill, New York, 1990).
  3. W. Marcus, J. Hickey, “A CMOS batcher and banyan set for B-ISDN,” in Proceedings of the IEEE International Conference on Solid-State Circuits (Institute of Electrical and Electronics Engineers, New York, 1990), pp. 32–33.
    [CrossRef]
  4. S. C. Knauer, A. Huang, J. H. O’Neill, “Self-routing switching network,” in CMOS VLSI Design, N. Weste, K. Eshragian, eds. (Addison-Wesley, Reading, Mass., 1988), Chap. 9, pp. 424–448.
  5. J. Hickey, W. Marcus, “Implementation of a high-speed ATM packet switch using CMOS VLSI,” in Proceedings of the IEEE International Symposium on Switching (Institute of Electrical and Electronics Engineers, New York, 1990), pp. 75–84.
    [CrossRef]
  6. H. S. Hinton, “Architectural considerations for photonic switching networks,” IEEE J. Select. Areas Commun. 6, 1209–1226 (1988).
    [CrossRef]
  7. F. Kiamilev, P. Marchand, A. V. Krishnamoorthy, S. Esener, S. H. Lee, “Performance comparison between optoelectronic and VLSI multistage interconnection networks,” EEEJ. Lightwave Tech. 9, 1674–1692 (1991).
    [CrossRef]
  8. M. Murdocca, T. J. Cloonan, “Optical design of a digital switch,” Appl. Opt. 28, 2505–2517 (1989).
    [CrossRef] [PubMed]
  9. M. R. Feldman, S. C. Esener, C. C. Guest, S. H. Lee, “Comparison between electrical and free-space optical interconnects based on power and speed considerations,” Appl. Opt. 27, 1742–1751 (1988).
    [CrossRef] [PubMed]
  10. R. K. Kostuk, J. W. Goodman, L. Hesselink, “Optical imaging applied to microelectronic chip-to-chip interconnections,” Appl. Opt. 24, 2851–2858 (1985).
    [CrossRef] [PubMed]
  11. D. M. Dias, J. R. Jump, “Analysis and simulation of buffered delta networks,” IEEE Trans. Comput. C-30, 273–282 (1981).
    [CrossRef]
  12. C. P. Kruskal, M. Snir, “The performance of multistage interconnection networks for multiprocessors,” IEEE Trans. Comput. C-32, 1091–1098 (1983).
    [CrossRef]
  13. R. Paturi, D. T. Lu, J. E. Ford, S. C. Esener, S. H. Lee, “Parallel algorithm for expander graphs for optical computing,” Appl. Opt. 30, 917–927 (1991).
    [CrossRef] [PubMed]
  14. H. S. Stone, “Parallel processing with the perfect shuffle,” IEEE Trans. Comput. C-20, 81–89 (1971).
    [CrossRef]
  15. D. H. Lawrie, “Access and alignment of data in an array processor,” IEEE Trans. Comput. C-24, 1145–1155 (1975).
    [CrossRef]
  16. A. Lohmann, G. Stucke, W. Stork, “Optical perfect shuffle,” Appl. Opt. 25, 1530–1531 (1986).
    [CrossRef] [PubMed]
  17. S. H. Lin, T. F. Krille, J. F. Walkup, “2-D optical multistage interconnection networks,” in Digital Optical Computing, R. Arrathoon, ed., Proc. Soc. Photo-Opt. Instrum. Eng.752, 209–216 (1987).
  18. J. Jahns, M. J. Murdocca, “Crossover networks and their optical implementation,” Appl. Opt. 27, 3155–3160 (1988).
    [CrossRef] [PubMed]
  19. J. Patel, “Performance of processor-memory interconnections for multiprocessors,” IEEE Trans. Comput. C-30, 771–780 (1981).
    [CrossRef]
  20. W. Dobblelaere, D. Huang, M. S. Unlu, H. Morkoc, “AlGaAs/GaAs multiple quantum well reflection modulators grown on Si substrates,” Appl. Phys. Lett. 55, 94–96 (1988).
    [CrossRef]
  21. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI (Addison-Wesley, Reading, Mass., 1990), Chap. 5.
  22. K. S. Urquhart, S. H. Lee, C. C. Guest, M. R. Feldman, H. Farhoosh, “Computer aided design of computer generated holograms for electron beam fabrication,” Appl. Opt. 28, 3387–3396 (1989).
    [CrossRef] [PubMed]
  23. K. S. Urquhart, H. Farhoosh, S. H. Lee, “Diffractive lenses utilizing cylindrical fresnel zone plates,” in Computer and Optically Formed Holographic Optics, I. Cindrich, S. H. Lee, eds., Proc. Soc. Photo-Opt. Instrum. Eng.1211, 184–190 (1990).
  24. D. A. B. Miller, “Optoelectronic applications of quantum wells,” Opt. Photon. News 1(10), 7–20 (1990).
    [CrossRef]
  25. A. Dickinson, M. E. Prise, “Free-space optical interconnection scheme,” Appl. Opt. 29, 2001–2005 (1990).
    [CrossRef] [PubMed]
  26. W. J. Dally, “A VLSI architecture for concurrent data structures,” Department of Computer Sciences Tech. Rep. 5209, TR:86 (California Institute of Technology, Pasadena, Calif., 1986).
  27. C. D. Thompson, “A complexity theory for VLSI,” Ph.D. dissertation (Carnegie-Mellon University, Pittsburgh, Pa., 1980).
  28. A. Lohmann, “What classical optics can do for the digital optical computer,” Appl. Opt. 25, 1543–1549 (1986).
    [CrossRef] [PubMed]
  29. G. Lohmann, A. Lohmann, “Optical interconnection network utilizing diffraction gratings,” Opt. Eng. 27, 893–900 (1988).
  30. Q. W. Song, F. T. Yu, “Generalized perfect shuffle using optical spatial filtering,” Appl. Opt. 27, 1222–1223 (1988).
    [CrossRef] [PubMed]
  31. K. Brenner, A. Huang, “Optical implementations of the perfect shuffle interconnection,” Appl. Opt. 27, 135–137 (1988).
    [CrossRef] [PubMed]
  32. C. Stirk, R. A. Athale, M. W. Haney, “Folded perfect shuffle optical processor,” Appl. Opt. 27, 202–203 (1988).
    [CrossRef] [PubMed]
  33. A. Sawchuk, I. Glaser, “Geometries for optical implementations of the perfect shuffle,” in Optical Computing ’88, P. Chavel, J. W. Goodman, G. Roblin, eds., Proc. Soc. Photo-Opt. Instrum. Eng.963, 270–282 (1988).
    [CrossRef]
  34. M. W. Haney, J. J. Levy, “Low loss free-space perfect shuffle network,” presented at the 1990 International Topical Meeting on Optical Computing.
  35. M. W. Haney, “Optoelectronic shuffle exchange network for multiprocessing architectures,” in OSA Annual Meeting, Vol. 15 of 1990 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1990), p. 87.
  36. G. J. Swanson, “Binary optics technology: the theory and design of multi-level diffractive elements,” DARPA Tech. Rep. 854 (Defense Advanced Research Projects Agency, Washington, D.C., 1989).
  37. K. S. Urquhart, P. Marchand, Y. Fainman, S. H. Lee, “Design of free-space optical interconnection modules utilizing diffractive optics,” submitted to Appl. Opt.
  38. Code V is a registered trademark of Optical Research Associates, Pasadena, Ca.
  39. R. E. Knowlden, “Binary optics: theory, design, and applications,” in SPIE Short Course Handbook, SPIE Annual Meeting, 1990 (Society of Photo-Optical Instrumentation Engineers, Bellingham, Wash., 1990).
  40. A. L. Lentine, F. B. McCormick, R. A. Novotny, L. M. F. Chirovsky, L. A. D’Asaro, R. F. Kopf, J. M. Kuo, G. D. Boyd, “A 2 kbit array of symmetric self-electrooptic effect devices,” IEEE Photon. Tech. Lett. 2, 51–53 (1990).
    [CrossRef]
  41. T. H. Lin, A. Ersen, J. H. Wang, S. Dasgupta, S. Esener, S. H. Lee, “Two-dimensional spatial light modulators fabricated in Si/PLZT,” Appl. Opt. 29, 1595–1603 (1990).
    [CrossRef] [PubMed]
  42. K. Batcher, “Sorting network and their applications,” presented at the American Federation of Information Processing Societies 1968 Spring Joint Computer Conference.
  43. J. Goodman, Introduction to Fourier Optics (McGraw-Hill, New York, 1968).

1991

F. Kiamilev, P. Marchand, A. V. Krishnamoorthy, S. Esener, S. H. Lee, “Performance comparison between optoelectronic and VLSI multistage interconnection networks,” EEEJ. Lightwave Tech. 9, 1674–1692 (1991).
[CrossRef]

R. Paturi, D. T. Lu, J. E. Ford, S. C. Esener, S. H. Lee, “Parallel algorithm for expander graphs for optical computing,” Appl. Opt. 30, 917–927 (1991).
[CrossRef] [PubMed]

1990

T. H. Lin, A. Ersen, J. H. Wang, S. Dasgupta, S. Esener, S. H. Lee, “Two-dimensional spatial light modulators fabricated in Si/PLZT,” Appl. Opt. 29, 1595–1603 (1990).
[CrossRef] [PubMed]

A. Dickinson, M. E. Prise, “Free-space optical interconnection scheme,” Appl. Opt. 29, 2001–2005 (1990).
[CrossRef] [PubMed]

D. A. B. Miller, “Optoelectronic applications of quantum wells,” Opt. Photon. News 1(10), 7–20 (1990).
[CrossRef]

A. L. Lentine, F. B. McCormick, R. A. Novotny, L. M. F. Chirovsky, L. A. D’Asaro, R. F. Kopf, J. M. Kuo, G. D. Boyd, “A 2 kbit array of symmetric self-electrooptic effect devices,” IEEE Photon. Tech. Lett. 2, 51–53 (1990).
[CrossRef]

1989

1988

1986

1985

1983

C. P. Kruskal, M. Snir, “The performance of multistage interconnection networks for multiprocessors,” IEEE Trans. Comput. C-32, 1091–1098 (1983).
[CrossRef]

1981

D. M. Dias, J. R. Jump, “Analysis and simulation of buffered delta networks,” IEEE Trans. Comput. C-30, 273–282 (1981).
[CrossRef]

J. Patel, “Performance of processor-memory interconnections for multiprocessors,” IEEE Trans. Comput. C-30, 771–780 (1981).
[CrossRef]

1975

D. H. Lawrie, “Access and alignment of data in an array processor,” IEEE Trans. Comput. C-24, 1145–1155 (1975).
[CrossRef]

1971

H. S. Stone, “Parallel processing with the perfect shuffle,” IEEE Trans. Comput. C-20, 81–89 (1971).
[CrossRef]

Athale, R. A.

Bakoglu, H. B.

H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI (Addison-Wesley, Reading, Mass., 1990), Chap. 5.

Batcher, K.

K. Batcher, “Sorting network and their applications,” presented at the American Federation of Information Processing Societies 1968 Spring Joint Computer Conference.

Boyd, G. D.

A. L. Lentine, F. B. McCormick, R. A. Novotny, L. M. F. Chirovsky, L. A. D’Asaro, R. F. Kopf, J. M. Kuo, G. D. Boyd, “A 2 kbit array of symmetric self-electrooptic effect devices,” IEEE Photon. Tech. Lett. 2, 51–53 (1990).
[CrossRef]

Brenner, K.

Chirovsky, L. M. F.

A. L. Lentine, F. B. McCormick, R. A. Novotny, L. M. F. Chirovsky, L. A. D’Asaro, R. F. Kopf, J. M. Kuo, G. D. Boyd, “A 2 kbit array of symmetric self-electrooptic effect devices,” IEEE Photon. Tech. Lett. 2, 51–53 (1990).
[CrossRef]

Cloonan, T. J.

D’Asaro, L. A.

A. L. Lentine, F. B. McCormick, R. A. Novotny, L. M. F. Chirovsky, L. A. D’Asaro, R. F. Kopf, J. M. Kuo, G. D. Boyd, “A 2 kbit array of symmetric self-electrooptic effect devices,” IEEE Photon. Tech. Lett. 2, 51–53 (1990).
[CrossRef]

Dally, W. J.

W. J. Dally, “A VLSI architecture for concurrent data structures,” Department of Computer Sciences Tech. Rep. 5209, TR:86 (California Institute of Technology, Pasadena, Calif., 1986).

Dasgupta, S.

Decegama, A. L.

A. L. Decegama, Parallel Processing Architectures and VLSI Hardware (Prentice-Hall, Englewood Cliffs, N.J., 1989), Vol. 1, Chap. 1.

Dias, D. M.

D. M. Dias, J. R. Jump, “Analysis and simulation of buffered delta networks,” IEEE Trans. Comput. C-30, 273–282 (1981).
[CrossRef]

Dickinson, A.

Dobblelaere, W.

W. Dobblelaere, D. Huang, M. S. Unlu, H. Morkoc, “AlGaAs/GaAs multiple quantum well reflection modulators grown on Si substrates,” Appl. Phys. Lett. 55, 94–96 (1988).
[CrossRef]

Ersen, A.

Esener, S.

F. Kiamilev, P. Marchand, A. V. Krishnamoorthy, S. Esener, S. H. Lee, “Performance comparison between optoelectronic and VLSI multistage interconnection networks,” EEEJ. Lightwave Tech. 9, 1674–1692 (1991).
[CrossRef]

T. H. Lin, A. Ersen, J. H. Wang, S. Dasgupta, S. Esener, S. H. Lee, “Two-dimensional spatial light modulators fabricated in Si/PLZT,” Appl. Opt. 29, 1595–1603 (1990).
[CrossRef] [PubMed]

Esener, S. C.

Fainman, Y.

K. S. Urquhart, P. Marchand, Y. Fainman, S. H. Lee, “Design of free-space optical interconnection modules utilizing diffractive optics,” submitted to Appl. Opt.

Farhoosh, H.

K. S. Urquhart, S. H. Lee, C. C. Guest, M. R. Feldman, H. Farhoosh, “Computer aided design of computer generated holograms for electron beam fabrication,” Appl. Opt. 28, 3387–3396 (1989).
[CrossRef] [PubMed]

K. S. Urquhart, H. Farhoosh, S. H. Lee, “Diffractive lenses utilizing cylindrical fresnel zone plates,” in Computer and Optically Formed Holographic Optics, I. Cindrich, S. H. Lee, eds., Proc. Soc. Photo-Opt. Instrum. Eng.1211, 184–190 (1990).

Feldman, M. R.

Ford, J. E.

Glaser, I.

A. Sawchuk, I. Glaser, “Geometries for optical implementations of the perfect shuffle,” in Optical Computing ’88, P. Chavel, J. W. Goodman, G. Roblin, eds., Proc. Soc. Photo-Opt. Instrum. Eng.963, 270–282 (1988).
[CrossRef]

Goodman, J.

J. Goodman, Introduction to Fourier Optics (McGraw-Hill, New York, 1968).

Goodman, J. W.

Guest, C. C.

Haney, M. W.

C. Stirk, R. A. Athale, M. W. Haney, “Folded perfect shuffle optical processor,” Appl. Opt. 27, 202–203 (1988).
[CrossRef] [PubMed]

M. W. Haney, J. J. Levy, “Low loss free-space perfect shuffle network,” presented at the 1990 International Topical Meeting on Optical Computing.

M. W. Haney, “Optoelectronic shuffle exchange network for multiprocessing architectures,” in OSA Annual Meeting, Vol. 15 of 1990 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1990), p. 87.

Hesselink, L.

Hickey, J.

W. Marcus, J. Hickey, “A CMOS batcher and banyan set for B-ISDN,” in Proceedings of the IEEE International Conference on Solid-State Circuits (Institute of Electrical and Electronics Engineers, New York, 1990), pp. 32–33.
[CrossRef]

J. Hickey, W. Marcus, “Implementation of a high-speed ATM packet switch using CMOS VLSI,” in Proceedings of the IEEE International Symposium on Switching (Institute of Electrical and Electronics Engineers, New York, 1990), pp. 75–84.
[CrossRef]

Hinton, H. S.

H. S. Hinton, “Architectural considerations for photonic switching networks,” IEEE J. Select. Areas Commun. 6, 1209–1226 (1988).
[CrossRef]

Huang, A.

K. Brenner, A. Huang, “Optical implementations of the perfect shuffle interconnection,” Appl. Opt. 27, 135–137 (1988).
[CrossRef] [PubMed]

S. C. Knauer, A. Huang, J. H. O’Neill, “Self-routing switching network,” in CMOS VLSI Design, N. Weste, K. Eshragian, eds. (Addison-Wesley, Reading, Mass., 1988), Chap. 9, pp. 424–448.

Huang, D.

W. Dobblelaere, D. Huang, M. S. Unlu, H. Morkoc, “AlGaAs/GaAs multiple quantum well reflection modulators grown on Si substrates,” Appl. Phys. Lett. 55, 94–96 (1988).
[CrossRef]

Jahns, J.

Jump, J. R.

D. M. Dias, J. R. Jump, “Analysis and simulation of buffered delta networks,” IEEE Trans. Comput. C-30, 273–282 (1981).
[CrossRef]

Kiamilev, F.

F. Kiamilev, P. Marchand, A. V. Krishnamoorthy, S. Esener, S. H. Lee, “Performance comparison between optoelectronic and VLSI multistage interconnection networks,” EEEJ. Lightwave Tech. 9, 1674–1692 (1991).
[CrossRef]

Knauer, S. C.

S. C. Knauer, A. Huang, J. H. O’Neill, “Self-routing switching network,” in CMOS VLSI Design, N. Weste, K. Eshragian, eds. (Addison-Wesley, Reading, Mass., 1988), Chap. 9, pp. 424–448.

Knowlden, R. E.

R. E. Knowlden, “Binary optics: theory, design, and applications,” in SPIE Short Course Handbook, SPIE Annual Meeting, 1990 (Society of Photo-Optical Instrumentation Engineers, Bellingham, Wash., 1990).

Kopf, R. F.

A. L. Lentine, F. B. McCormick, R. A. Novotny, L. M. F. Chirovsky, L. A. D’Asaro, R. F. Kopf, J. M. Kuo, G. D. Boyd, “A 2 kbit array of symmetric self-electrooptic effect devices,” IEEE Photon. Tech. Lett. 2, 51–53 (1990).
[CrossRef]

Kostuk, R. K.

Krille, T. F.

S. H. Lin, T. F. Krille, J. F. Walkup, “2-D optical multistage interconnection networks,” in Digital Optical Computing, R. Arrathoon, ed., Proc. Soc. Photo-Opt. Instrum. Eng.752, 209–216 (1987).

Krishnamoorthy, A. V.

F. Kiamilev, P. Marchand, A. V. Krishnamoorthy, S. Esener, S. H. Lee, “Performance comparison between optoelectronic and VLSI multistage interconnection networks,” EEEJ. Lightwave Tech. 9, 1674–1692 (1991).
[CrossRef]

Kruskal, C. P.

C. P. Kruskal, M. Snir, “The performance of multistage interconnection networks for multiprocessors,” IEEE Trans. Comput. C-32, 1091–1098 (1983).
[CrossRef]

Kuo, J. M.

A. L. Lentine, F. B. McCormick, R. A. Novotny, L. M. F. Chirovsky, L. A. D’Asaro, R. F. Kopf, J. M. Kuo, G. D. Boyd, “A 2 kbit array of symmetric self-electrooptic effect devices,” IEEE Photon. Tech. Lett. 2, 51–53 (1990).
[CrossRef]

Lawrie, D. H.

D. H. Lawrie, “Access and alignment of data in an array processor,” IEEE Trans. Comput. C-24, 1145–1155 (1975).
[CrossRef]

Lee, S. H.

F. Kiamilev, P. Marchand, A. V. Krishnamoorthy, S. Esener, S. H. Lee, “Performance comparison between optoelectronic and VLSI multistage interconnection networks,” EEEJ. Lightwave Tech. 9, 1674–1692 (1991).
[CrossRef]

R. Paturi, D. T. Lu, J. E. Ford, S. C. Esener, S. H. Lee, “Parallel algorithm for expander graphs for optical computing,” Appl. Opt. 30, 917–927 (1991).
[CrossRef] [PubMed]

T. H. Lin, A. Ersen, J. H. Wang, S. Dasgupta, S. Esener, S. H. Lee, “Two-dimensional spatial light modulators fabricated in Si/PLZT,” Appl. Opt. 29, 1595–1603 (1990).
[CrossRef] [PubMed]

K. S. Urquhart, S. H. Lee, C. C. Guest, M. R. Feldman, H. Farhoosh, “Computer aided design of computer generated holograms for electron beam fabrication,” Appl. Opt. 28, 3387–3396 (1989).
[CrossRef] [PubMed]

M. R. Feldman, S. C. Esener, C. C. Guest, S. H. Lee, “Comparison between electrical and free-space optical interconnects based on power and speed considerations,” Appl. Opt. 27, 1742–1751 (1988).
[CrossRef] [PubMed]

K. S. Urquhart, P. Marchand, Y. Fainman, S. H. Lee, “Design of free-space optical interconnection modules utilizing diffractive optics,” submitted to Appl. Opt.

K. S. Urquhart, H. Farhoosh, S. H. Lee, “Diffractive lenses utilizing cylindrical fresnel zone plates,” in Computer and Optically Formed Holographic Optics, I. Cindrich, S. H. Lee, eds., Proc. Soc. Photo-Opt. Instrum. Eng.1211, 184–190 (1990).

Lentine, A. L.

A. L. Lentine, F. B. McCormick, R. A. Novotny, L. M. F. Chirovsky, L. A. D’Asaro, R. F. Kopf, J. M. Kuo, G. D. Boyd, “A 2 kbit array of symmetric self-electrooptic effect devices,” IEEE Photon. Tech. Lett. 2, 51–53 (1990).
[CrossRef]

Levy, J. J.

M. W. Haney, J. J. Levy, “Low loss free-space perfect shuffle network,” presented at the 1990 International Topical Meeting on Optical Computing.

Lin, S. H.

S. H. Lin, T. F. Krille, J. F. Walkup, “2-D optical multistage interconnection networks,” in Digital Optical Computing, R. Arrathoon, ed., Proc. Soc. Photo-Opt. Instrum. Eng.752, 209–216 (1987).

Lin, T. H.

Lohmann, A.

Lohmann, G.

G. Lohmann, A. Lohmann, “Optical interconnection network utilizing diffraction gratings,” Opt. Eng. 27, 893–900 (1988).

Lu, D. T.

Marchand, P.

F. Kiamilev, P. Marchand, A. V. Krishnamoorthy, S. Esener, S. H. Lee, “Performance comparison between optoelectronic and VLSI multistage interconnection networks,” EEEJ. Lightwave Tech. 9, 1674–1692 (1991).
[CrossRef]

K. S. Urquhart, P. Marchand, Y. Fainman, S. H. Lee, “Design of free-space optical interconnection modules utilizing diffractive optics,” submitted to Appl. Opt.

Marcus, W.

W. Marcus, J. Hickey, “A CMOS batcher and banyan set for B-ISDN,” in Proceedings of the IEEE International Conference on Solid-State Circuits (Institute of Electrical and Electronics Engineers, New York, 1990), pp. 32–33.
[CrossRef]

J. Hickey, W. Marcus, “Implementation of a high-speed ATM packet switch using CMOS VLSI,” in Proceedings of the IEEE International Symposium on Switching (Institute of Electrical and Electronics Engineers, New York, 1990), pp. 75–84.
[CrossRef]

McCormick, F. B.

A. L. Lentine, F. B. McCormick, R. A. Novotny, L. M. F. Chirovsky, L. A. D’Asaro, R. F. Kopf, J. M. Kuo, G. D. Boyd, “A 2 kbit array of symmetric self-electrooptic effect devices,” IEEE Photon. Tech. Lett. 2, 51–53 (1990).
[CrossRef]

Miller, D. A. B.

D. A. B. Miller, “Optoelectronic applications of quantum wells,” Opt. Photon. News 1(10), 7–20 (1990).
[CrossRef]

Morkoc, H.

W. Dobblelaere, D. Huang, M. S. Unlu, H. Morkoc, “AlGaAs/GaAs multiple quantum well reflection modulators grown on Si substrates,” Appl. Phys. Lett. 55, 94–96 (1988).
[CrossRef]

Murdocca, M.

Murdocca, M. J.

Novotny, R. A.

A. L. Lentine, F. B. McCormick, R. A. Novotny, L. M. F. Chirovsky, L. A. D’Asaro, R. F. Kopf, J. M. Kuo, G. D. Boyd, “A 2 kbit array of symmetric self-electrooptic effect devices,” IEEE Photon. Tech. Lett. 2, 51–53 (1990).
[CrossRef]

O’Neill, J. H.

S. C. Knauer, A. Huang, J. H. O’Neill, “Self-routing switching network,” in CMOS VLSI Design, N. Weste, K. Eshragian, eds. (Addison-Wesley, Reading, Mass., 1988), Chap. 9, pp. 424–448.

Patel, J.

J. Patel, “Performance of processor-memory interconnections for multiprocessors,” IEEE Trans. Comput. C-30, 771–780 (1981).
[CrossRef]

Paturi, R.

Prise, M. E.

Sawchuk, A.

A. Sawchuk, I. Glaser, “Geometries for optical implementations of the perfect shuffle,” in Optical Computing ’88, P. Chavel, J. W. Goodman, G. Roblin, eds., Proc. Soc. Photo-Opt. Instrum. Eng.963, 270–282 (1988).
[CrossRef]

Siegel, H. J.

H. J. Siegel, Interconnection Networks for Large-Scale Parallel Processing, 2nd ed. (McGraw-Hill, New York, 1990).

Snir, M.

C. P. Kruskal, M. Snir, “The performance of multistage interconnection networks for multiprocessors,” IEEE Trans. Comput. C-32, 1091–1098 (1983).
[CrossRef]

Song, Q. W.

Stirk, C.

Stone, H. S.

H. S. Stone, “Parallel processing with the perfect shuffle,” IEEE Trans. Comput. C-20, 81–89 (1971).
[CrossRef]

Stork, W.

Stucke, G.

Swanson, G. J.

G. J. Swanson, “Binary optics technology: the theory and design of multi-level diffractive elements,” DARPA Tech. Rep. 854 (Defense Advanced Research Projects Agency, Washington, D.C., 1989).

Thompson, C. D.

C. D. Thompson, “A complexity theory for VLSI,” Ph.D. dissertation (Carnegie-Mellon University, Pittsburgh, Pa., 1980).

Unlu, M. S.

W. Dobblelaere, D. Huang, M. S. Unlu, H. Morkoc, “AlGaAs/GaAs multiple quantum well reflection modulators grown on Si substrates,” Appl. Phys. Lett. 55, 94–96 (1988).
[CrossRef]

Urquhart, K. S.

K. S. Urquhart, S. H. Lee, C. C. Guest, M. R. Feldman, H. Farhoosh, “Computer aided design of computer generated holograms for electron beam fabrication,” Appl. Opt. 28, 3387–3396 (1989).
[CrossRef] [PubMed]

K. S. Urquhart, H. Farhoosh, S. H. Lee, “Diffractive lenses utilizing cylindrical fresnel zone plates,” in Computer and Optically Formed Holographic Optics, I. Cindrich, S. H. Lee, eds., Proc. Soc. Photo-Opt. Instrum. Eng.1211, 184–190 (1990).

K. S. Urquhart, P. Marchand, Y. Fainman, S. H. Lee, “Design of free-space optical interconnection modules utilizing diffractive optics,” submitted to Appl. Opt.

Walkup, J. F.

S. H. Lin, T. F. Krille, J. F. Walkup, “2-D optical multistage interconnection networks,” in Digital Optical Computing, R. Arrathoon, ed., Proc. Soc. Photo-Opt. Instrum. Eng.752, 209–216 (1987).

Wang, J. H.

Yu, F. T.

Appl. Opt.

R. K. Kostuk, J. W. Goodman, L. Hesselink, “Optical imaging applied to microelectronic chip-to-chip interconnections,” Appl. Opt. 24, 2851–2858 (1985).
[CrossRef] [PubMed]

A. Lohmann, “What classical optics can do for the digital optical computer,” Appl. Opt. 25, 1543–1549 (1986).
[CrossRef] [PubMed]

K. Brenner, A. Huang, “Optical implementations of the perfect shuffle interconnection,” Appl. Opt. 27, 135–137 (1988).
[CrossRef] [PubMed]

Q. W. Song, F. T. Yu, “Generalized perfect shuffle using optical spatial filtering,” Appl. Opt. 27, 1222–1223 (1988).
[CrossRef] [PubMed]

M. R. Feldman, S. C. Esener, C. C. Guest, S. H. Lee, “Comparison between electrical and free-space optical interconnects based on power and speed considerations,” Appl. Opt. 27, 1742–1751 (1988).
[CrossRef] [PubMed]

M. Murdocca, T. J. Cloonan, “Optical design of a digital switch,” Appl. Opt. 28, 2505–2517 (1989).
[CrossRef] [PubMed]

K. S. Urquhart, S. H. Lee, C. C. Guest, M. R. Feldman, H. Farhoosh, “Computer aided design of computer generated holograms for electron beam fabrication,” Appl. Opt. 28, 3387–3396 (1989).
[CrossRef] [PubMed]

T. H. Lin, A. Ersen, J. H. Wang, S. Dasgupta, S. Esener, S. H. Lee, “Two-dimensional spatial light modulators fabricated in Si/PLZT,” Appl. Opt. 29, 1595–1603 (1990).
[CrossRef] [PubMed]

A. Dickinson, M. E. Prise, “Free-space optical interconnection scheme,” Appl. Opt. 29, 2001–2005 (1990).
[CrossRef] [PubMed]

R. Paturi, D. T. Lu, J. E. Ford, S. C. Esener, S. H. Lee, “Parallel algorithm for expander graphs for optical computing,” Appl. Opt. 30, 917–927 (1991).
[CrossRef] [PubMed]

J. Jahns, M. J. Murdocca, “Crossover networks and their optical implementation,” Appl. Opt. 27, 3155–3160 (1988).
[CrossRef] [PubMed]

A. Lohmann, G. Stucke, W. Stork, “Optical perfect shuffle,” Appl. Opt. 25, 1530–1531 (1986).
[CrossRef] [PubMed]

C. Stirk, R. A. Athale, M. W. Haney, “Folded perfect shuffle optical processor,” Appl. Opt. 27, 202–203 (1988).
[CrossRef] [PubMed]

Appl. Phys. Lett.

W. Dobblelaere, D. Huang, M. S. Unlu, H. Morkoc, “AlGaAs/GaAs multiple quantum well reflection modulators grown on Si substrates,” Appl. Phys. Lett. 55, 94–96 (1988).
[CrossRef]

EEEJ. Lightwave Tech.

F. Kiamilev, P. Marchand, A. V. Krishnamoorthy, S. Esener, S. H. Lee, “Performance comparison between optoelectronic and VLSI multistage interconnection networks,” EEEJ. Lightwave Tech. 9, 1674–1692 (1991).
[CrossRef]

IEEE J. Select. Areas Commun.

H. S. Hinton, “Architectural considerations for photonic switching networks,” IEEE J. Select. Areas Commun. 6, 1209–1226 (1988).
[CrossRef]

IEEE Photon. Tech. Lett.

A. L. Lentine, F. B. McCormick, R. A. Novotny, L. M. F. Chirovsky, L. A. D’Asaro, R. F. Kopf, J. M. Kuo, G. D. Boyd, “A 2 kbit array of symmetric self-electrooptic effect devices,” IEEE Photon. Tech. Lett. 2, 51–53 (1990).
[CrossRef]

IEEE Trans. Comput.

J. Patel, “Performance of processor-memory interconnections for multiprocessors,” IEEE Trans. Comput. C-30, 771–780 (1981).
[CrossRef]

D. M. Dias, J. R. Jump, “Analysis and simulation of buffered delta networks,” IEEE Trans. Comput. C-30, 273–282 (1981).
[CrossRef]

C. P. Kruskal, M. Snir, “The performance of multistage interconnection networks for multiprocessors,” IEEE Trans. Comput. C-32, 1091–1098 (1983).
[CrossRef]

H. S. Stone, “Parallel processing with the perfect shuffle,” IEEE Trans. Comput. C-20, 81–89 (1971).
[CrossRef]

D. H. Lawrie, “Access and alignment of data in an array processor,” IEEE Trans. Comput. C-24, 1145–1155 (1975).
[CrossRef]

Opt. Eng.

G. Lohmann, A. Lohmann, “Optical interconnection network utilizing diffraction gratings,” Opt. Eng. 27, 893–900 (1988).

Opt. Photon. News

D. A. B. Miller, “Optoelectronic applications of quantum wells,” Opt. Photon. News 1(10), 7–20 (1990).
[CrossRef]

Other

W. J. Dally, “A VLSI architecture for concurrent data structures,” Department of Computer Sciences Tech. Rep. 5209, TR:86 (California Institute of Technology, Pasadena, Calif., 1986).

C. D. Thompson, “A complexity theory for VLSI,” Ph.D. dissertation (Carnegie-Mellon University, Pittsburgh, Pa., 1980).

A. Sawchuk, I. Glaser, “Geometries for optical implementations of the perfect shuffle,” in Optical Computing ’88, P. Chavel, J. W. Goodman, G. Roblin, eds., Proc. Soc. Photo-Opt. Instrum. Eng.963, 270–282 (1988).
[CrossRef]

M. W. Haney, J. J. Levy, “Low loss free-space perfect shuffle network,” presented at the 1990 International Topical Meeting on Optical Computing.

M. W. Haney, “Optoelectronic shuffle exchange network for multiprocessing architectures,” in OSA Annual Meeting, Vol. 15 of 1990 OSA Technical Digest Series (Optical Society of America, Washington, D.C., 1990), p. 87.

G. J. Swanson, “Binary optics technology: the theory and design of multi-level diffractive elements,” DARPA Tech. Rep. 854 (Defense Advanced Research Projects Agency, Washington, D.C., 1989).

K. S. Urquhart, P. Marchand, Y. Fainman, S. H. Lee, “Design of free-space optical interconnection modules utilizing diffractive optics,” submitted to Appl. Opt.

Code V is a registered trademark of Optical Research Associates, Pasadena, Ca.

R. E. Knowlden, “Binary optics: theory, design, and applications,” in SPIE Short Course Handbook, SPIE Annual Meeting, 1990 (Society of Photo-Optical Instrumentation Engineers, Bellingham, Wash., 1990).

S. H. Lin, T. F. Krille, J. F. Walkup, “2-D optical multistage interconnection networks,” in Digital Optical Computing, R. Arrathoon, ed., Proc. Soc. Photo-Opt. Instrum. Eng.752, 209–216 (1987).

A. L. Decegama, Parallel Processing Architectures and VLSI Hardware (Prentice-Hall, Englewood Cliffs, N.J., 1989), Vol. 1, Chap. 1.

H. J. Siegel, Interconnection Networks for Large-Scale Parallel Processing, 2nd ed. (McGraw-Hill, New York, 1990).

W. Marcus, J. Hickey, “A CMOS batcher and banyan set for B-ISDN,” in Proceedings of the IEEE International Conference on Solid-State Circuits (Institute of Electrical and Electronics Engineers, New York, 1990), pp. 32–33.
[CrossRef]

S. C. Knauer, A. Huang, J. H. O’Neill, “Self-routing switching network,” in CMOS VLSI Design, N. Weste, K. Eshragian, eds. (Addison-Wesley, Reading, Mass., 1988), Chap. 9, pp. 424–448.

J. Hickey, W. Marcus, “Implementation of a high-speed ATM packet switch using CMOS VLSI,” in Proceedings of the IEEE International Symposium on Switching (Institute of Electrical and Electronics Engineers, New York, 1990), pp. 75–84.
[CrossRef]

K. Batcher, “Sorting network and their applications,” presented at the American Federation of Information Processing Societies 1968 Spring Joint Computer Conference.

J. Goodman, Introduction to Fourier Optics (McGraw-Hill, New York, 1968).

H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI (Addison-Wesley, Reading, Mass., 1990), Chap. 5.

K. S. Urquhart, H. Farhoosh, S. H. Lee, “Diffractive lenses utilizing cylindrical fresnel zone plates,” in Computer and Optically Formed Holographic Optics, I. Cindrich, S. H. Lee, eds., Proc. Soc. Photo-Opt. Instrum. Eng.1211, 184–190 (1990).

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Figures (27)

Fig. 1
Fig. 1

2 × 2 bypass and exchange is the basic building block of a MIN. The inputs are either passed straight through or switched (exchanged).

Fig. 2
Fig. 2

Banyan interconnection network with 16 channels. The highlighted paths through the network illustrate the destination-based routing algorithm.

Fig. 3
Fig. 3

Gate-level design of the 2 × 2 bypass and exchange switch.

Fig. 4
Fig. 4

Mapping of the interconnection achieved by one stage of a 2-D shuffle-exchange network for N = 64 channels and K = 4 grain size.

Fig. 5
Fig. 5

Schematic of a K = 4 grain switch. A 2-D functional representation of the switch and its 1-D equivalent are also shown.

Fig. 6
Fig. 6

Shuffle-exchange interconnection network with N = 16 and K = 4. The highlighted path illustrates the 2-D destination-based routing algorithm.

Fig. 7
Fig. 7

Optoelectronic chip layout for the 2-D shuffle-exchange network. Detectors and modulators are uniformly spaced in the 2-D plane.

Fig. 8
Fig. 8

Traditional perfect-shuffle VLSI layout. This layout places inputs and outputs on the periphery of the network.

Fig. 9
Fig. 9

Perfect-shuffle network of size N = 16 with normal 2 × 2 bypass-exchange switches partitioned into half-switches.

Fig. 10
Fig. 10

2-D layout for the shuffle-exchange switch with size K = 16. Modulators and detectors are evenly distributed throughout the grain.

Fig. 11
Fig. 11

Comparison of the 2-D layout with conventional 1-D VLSI shuffle layouts. (a) The clock speed comparison shows that the 2-D layout (solid curve) outperforms a 1-D VLSI layout (dashed curve). (b) The area comparison shows that the 1-D VLSI layout (dashed curve) requires more area than the 2-D layout (solid curve).

Fig. 12
Fig. 12

Effect of the device count in the 2 × 2 bypass-exchange switch on the clock speed of the 2-D grain layout. The grain size K beyond which the clock speed starts decreasing is inversely proportional to the device count.

Fig. 13
Fig. 13

One-dimensional view of one stage of an N = 4096 channel, K = 16 grain-size shuffle-exchange interconnection showing A, B, A′, B′, i.e., the positions of the centers of the different imaging lenses.

Fig. 14
Fig. 14

Illustration of the underillumination of the dedicated lens of one of the edge modulators.

Fig. 15
Fig. 15

Geometric approximation for determining the worst-case optical efficiency of the 2-D shuffle interconnection for one of the edge modulators.

Fig. 16
Fig. 16

3-D plots of the basic grain-size study results showing (a) system bandwidth, Gbits/s; (b) system power, W; (c) system area, cm2; (d) system volume, cm3. These graphs are valid only at integer values of N and K, where K is a power of 4 and N = 2(K/2)i for i = 1,2,3, ….

Fig. 17
Fig. 17

Scalability considerations of the variable grain-size shuffle-exchange network showing (a) system electrical power consumption, W; (b) system optical power consumption, W; (c) optoelectronic chip width, cm; (d) on-chip power density, W (cm2).

Fig. 18
Fig. 18

Performance/cost metrics for the 2-D shuffle-exchange network with variable grain as a function of system size N and grain size K: (a) bandwidth/power, Gbits/s/W; (b) bandwidth–area, Gbits/S/cm2.

Fig. 19
Fig. 19

Effects of technology parameter variations on system cost showing (a) the effect of the number of phase levels of the diffractive elements on the optical power consumption per stage, N = 4096; (b) the effect of the number of phase levels of the diffractive elements on the system footprint area, N = 4096.

Fig. 20
Fig. 20

Effect of technology parameters on optimum grain size showing (a) bandwidth/power versus grain size K for various modulator driving voltages; (b) bandwidth/power versus grain size K for various detector powers; (c) bandwidth/power versus grain size for various VLSI CMOS minimum feature sizes.

Fig. 21
Fig. 21

System bandwidth/channel versus system size N for basic routing MIN (2 × 2) optimized for grain size, routing MIN with K × K contention-free switches (K = 4, 16, and 64), and a sorting MIN.

Fig. 22
Fig. 22

System bandwidth/power versus system size N for basic routing MIN (2 × 2) optimized for grain size, routing MIN with K × K contention-free switches (K = 4, 16, and 64), and a sorting MIN.

Fig. 23
Fig. 23

System bandwidth/area versus system size N for basic routing MIN (2 × 2) optimized for grain size, routing MIN with K × K contention-free switches (K = 4, 16, and 64), and a sorting MIN.

Fig. 24
Fig. 24

System power (cost) versus system bandwidth (performance) with N = 4096 for various optoelectronic (OE) MIN architectures based on the 2-D shuffle with variable grain K.

Fig. 25
Fig. 25

System area (cost) versus system bandwidth (performance) with N = 4096 for various optoelectronic MIN architectures based on the 2-D shuffle with variable grain K. Pure VLSI solutions are graphed for comparison. OE, optical element.

Fig. 26
Fig. 26

System volume (cost) versus system bandwidth (performance) with N = 4096 for various optoelectronic (OE) MIN architectures based on the 2-D shuffle with variable grain K.

Fig. 27
Fig. 27

Example of link address and link labeling for a perfect shuffle with size N = 8. Note that the bottom part defines the interconnection function for this network.

Tables (4)

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Table 1 Summary of Symbols and Definitions Used

Tables Icon

Table 2 VLSI Technology Parameters

Tables Icon

Table 3 Optoelectronic Techonolgy Parameters

Tables Icon

Table 4 Basic Grain-Size Study Resultsa

Equations (76)

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[ activity bit ] [ destination address ] [ data ] = A D log 2 N - 1 D 0 R k R 0 ,
[ ( N - i K - i K N - 1 ) , ( N - j K - i K N - 1 ) ] a ( i , j ) a mod N ,
T 90 % = 2.3 ( ½ R 0 C int L max + ½ R 0 C 0 + R int C 0 L max ) + R int C int L max 2 ,
A md = 4 A o ( C m C 0 - 1 ) λ e 2 ,
P mod = K L C m V m 2 F ,
P md = K L ( C m - C 0 ) V m 2 F ,
T 50 % = 0.7 R 0 C 0 ln ( C m C 0 ) .
A da = 20 A 0 λ e 2 .
P da = I diff V ,
A logic = A 0 ( M 2 ) log 2 K λ e 2 + A mod + A det + A md + A da .
A group = [ ( A logic ) 1 / 2 + K W λ e ] 2 ,
Δ = ( A logic ) 1 / 2 + K W λ e = [ A 0 ( M 2 ) log 2 K λ e 2 + A mod + A det + A md + A da ] 1 / 2 + K W λ e .
L max = ½ K Δ .
F max = [ 2.3 ( ½ R 0 C int L max + ½ R 0 C 0 + R int C 0 L max ) + R int C int L max 2 ] - 1 .
P pe = K [ P da + ( P mod + P md ) + F K pe log 2 K ( M 2 ) C 0 V 2 ] ,
P int = C int V 2 F K L ( 1 + 2 + 4 + , , K / 2 ) 2 Δ K ,
P int = K F K L C int ( K - 1 ) V 2 .
P grain = P int + P pe .
d 2 = K d 1 , f = K 1 + K d 1 ,
Δ c = [ ( N - 1 ) ( K + 1 ) ] Δ ,
( x i , y j ) = [ ± ( 2 i + 1 ) Δ c 2 , ± ( 2 j + 1 ) Δ c 2 ] ,             with i , j = 0 , , ( K 2 - 1 ) .
D i = N K Δ ,
D T = N Δ .
d mfs = λ Φ [ 1 + ( 2 f / # ) 2 ] 1 / 2 ,
f / # = Φ d mfs 2 λ .
d = [ ( N - 1 ) ( K + 1 ) + 1 2 ] Δ .
D eff = 2 d = [ ( 2 N + K - 1 ) ( K + 1 ) ] Δ .
f = f / # D eff = [ ( 2 N + K - 1 ) ( K + 1 ) ] Δ Φ d mfs 2 λ .
L = d 1 + d 2 = 1 + K K ( 2 N + K - 1 ) Δ Φ d mfs λ .
η wc = ( D / 2 + Δ / 2 ) 2 D 2 = 1 4 ( 1 + Δ D ) 2 ,
D = 2 d 1 tan θ = 2 N K Δ Φ d mfs δ ,
η wc = 1 4 ( 1 + δ K 2 N Φ d mfs ) 2 .
η 0 = η wc η d = 1 4 ( 1 + δ K 2 N Φ d mfs ) 2 sinc 2 ( 1 Φ ) .
δ λ sin [ tan - 1 ( 2 λ K δ det ) ] ,
D 2 D i - Δ 2 ,
N K Φ d mfs δ N K - 1 2 ,
δ Φ d mfs 1 - 1 2 K N .
A FP = D T L = 1 + K K [ 2 N + N ( K - 1 ) ] × Δ 2 Φ d mfs 2 λ [ log K ( N ) - 1 ] ,
V = D T A FP = 1 + K K [ 2 N 3 / 2 + N ( K - 1 ) ] Δ 3 × Φ d mfs 2 λ [ log K ( N ) - 1 ] .
F = F pe
F = F max = [ 2.3 ( ½ R 0 C int L max + ½ R 0 C 0 + R int C 0 L max ) + R int C int L max 2 ] - 1
B W 2 = F N P a = F N 4 log 2 N ,
P i = 1 - ( 1 - P i - 1 K ) K ,
P i = 1 ( K - 1 ) i 2 K + 1 P .
B W K = 2 K N F ( K - 1 ) log K ( N ) .
P e = N K log K ( N ) P grain .
P 0 = P det η 0 η mod η det N log K ( N ) .
P = P e + P 0 .
P abs = P abs ( mod off ) + P abs ( mod on ) + P abs ( det ) .
P abs = K 2 P det η mod η 0 η det + K 2 P det ( 1 - η mod ) η mod η 0 η det + K 2 P det η det .
P abs = K 2 P det η mod η 0 η det [ 2 + η mod ( η 0 - 1 ) ] .
D = P grain + P abs A grain .
S 0 [ X b m - 1 X ( b - 1 ) m X m - 1 X 0 ] = X b m - 2 X ( b - 1 ) m X b m - 1 X m - 2 X 0 X m - 1 ,
E 0 [ X b m - 1 X ( b - 1 ) m X m - 1 X 0 ] = X b m - 1 X ( b - 1 ) m X m - 1 X 0 ,
S i [ X b m - 1 X ( b - 1 ) m X m - 1 X 0 ] = X ( b - 1 ) m - 1 X ( b - 2 ) m X m - 1 X 0 X b m - 1 X b ( m - 1 ) ,
E i [ X b m - 1 X ( b - 1 ) m X m - 1 X 0 ] = X b m - 1 X ( b - 1 ) m X b - 1 X 0 ,
S i [ X b m - 1 X ( b - 1 ) m X m - 1 X 0 ] = X ( b - 1 ) m - 1 X ( b - 2 ) m X m - 1 X 0 X b m - 1 X b ( m - 1 ) ,
E i [ X b m - 1 X ( b - 1 ) m X m - 1 X 0 ] = X b m - 1 X ( b - 1 ) m X b - 1 X 0 ,
S ( X b m - 1 X 0 ) = X b m - 2 X 0 X b m - 1 ,
E ( X b m - 1 X 0 ) = X b m - 1 X 0 ,
E i ( X b m - 1 X 0 ) = X b m - 1 X b + 1 ( E S ) b ( X b X 0 ) ,
δ det = 2 λ d 2 D 2 + Δ 2 = 4 λ K d 1 D + Δ ,
D 2 d 1 = 2 λ K δ det - Δ 2 d 1 .
tan θ = D 2 d 1 θ = tan - 1 ( D 2 d 1 ) .
θ = tan - 1 ( 2 λ K δ det - Δ 2 d 1 ) .
sin θ = λ δ .
δ = λ sin θ = λ sin [ tan - 1 ( 2 λ K δ det - Δ 2 d 1 ) ] .
δ λ sin [ tan - 1 ( 2 λ K δ det ) ]
f / # = f D = Φ d mfs 2 λ .
δ im = 2 δ K 1 + δ K 2 N Φ d mfs 2 δ K .
D = 2 δ K .
f = D f / # = δ K Φ d mfs λ .
η = sinc 2 ( 1 Φ ) .
f = 16 δ K d mfs λ , η = 0.98.
L tot = L + f = ( 1 + K ) K N Δ Φ d mfs λ + 16 δ K d mfs λ ,
η tot = η 0 η = 1 4 ( 1 + δ K 2 N Φ d mfs ) 2 sinc 2 ( 1 Φ ) sinc 2 ( 1 Φ ) .

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