Abstract

Photodiodes are integrated into complementary metal-oxide semiconductor very-large-scale integration logic circuits to provide a hybrid interface between parallel-optical and electronic computing formats. This permits direct parallel transfer from an optical processor or storage element to a standard electronic system. The optical input beams may be viewed as control signals or as logical inputs that increase the system complexity and permit direct interaction of the electronic logic circuits with the optical beam states. Applications of the approach include hybrid optical-electronic logic gates, optical control of electronic data paths, and optically reconfigured very-large-scale integration circuits.

© 1992 Optical Society of America

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  1. A. Guha, J. Bristow, C. Sullivan, A. Hussain, “Optical interconnects for massively parallel architectures,” Appl. Opt. 29, 1077–1093 (1990).
    [CrossRef] [PubMed]
  2. T. Ichioka, J. Tanida, “Optical parallel logic gates using a shadow-casting system for optical digital computers,” Proc. IEEE 72, 787–801 (1984).
    [CrossRef]
  3. T. Sakano, K. Noguchi, T. Matsumoto, “Optical limits for spatial interconnection networks using 2-D optical array devices,” Appl. Opt. 29, 1094–1100 (1990).
    [CrossRef] [PubMed]
  4. M. R. Feldman, C. G. Guest, T. J. Drabik, S. C. Esener, “Comparison between electrical and free-space optical interconnects for fine grain processor arrays based on interconnect density capabilities,” Appl. Opt. 28, 3820–3829 (1989).
    [CrossRef] [PubMed]
  5. S. Fukushima, T. Kurokawa, H. Suzuki, “Optical implementation of parallel digital adder and subtractor,” Appl. Opt. 29, 2099–2106 (1990).
    [CrossRef] [PubMed]
  6. F. Lin, E. M. Strzelecki, T. Jannson, “Optical multiplanar VLSI interconnects based on multiplexed waveguide holograms,” Appl. Opt. 29, 1126–1133 (1990).
    [CrossRef] [PubMed]
  7. A. Dickenson, M. E. Prise, “Free-space optical interconnection scheme,” Appl. Opt. 29, 2001–2005 (1990).
    [CrossRef]
  8. L. A. Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C. Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, S. H. Lee, “Holographic optical interconnects for VLSI,” Opt. Eng. 25, 1109–1118 (1986).
  9. T. J. Drabik, “Optically interconnected parallel processor arrays,” Ph.D dissertation (Georgia Institute of Technology, Atlanta, Ga., 1989), pp. 112–120.
  10. J. P. Uyemura, Fundamentals of MOS Digital Integrated Circuits (Addison-Wesley, Reading, Mass., 1988).
  11. H. J. Krambeck, C. M. Lee, H. H. S. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits SC-17, 614–619 (1982).
    [CrossRef]
  12. G. G. Gonclaves, H. J. De Man, “NORA: A racefree dynamic CMOS technique for pipelined logic structures,” IEEE J. Solid-State Circuits SC-18, 261–266 (1983).
    [CrossRef]
  13. J. P. Uyemura, Circuit Design for CMOS VLSI (Kluwer Academic, Boston, Mass., 1992).
    [CrossRef]
  14. A. H. Sayles, J. P. Uyemura, “An optoelectronic CMOS memory circuit for parallel detection and storage of optical data,” IEEE J. Solid-State Circuits 26, 1110–1115, (1991).
    [CrossRef]
  15. A. H. Sayles, “Design of integrated CMOS circuits for parallel detection and storage of optical data,” Ph.D. dissertation (Georgia Institute of Technology, Atlanta, Ga., 1990).
  16. R. I. MacDonald, S. S. Lee, “Photodetector sensitivity control for weight-setting in optoelectronic neural networks,” Appl. Opt. 30, 176–179 (1991).
    [CrossRef] [PubMed]
  17. D. Psaltis, M. A. Neifeld, A. Yamamura, S. Kobayashi, “Optical memory disks in optical information processing,” Appl. Opt. 29, 2038–2057 (1990).
    [CrossRef] [PubMed]
  18. W. Zhang, K. Itho, J. Tanida, Y. Ichioka, “Hopfield model with multistage neurons and its optoelectronic implementation,” Appl. Opt. 30, 195–200 (1991).
    [CrossRef] [PubMed]
  19. P. J. de Groot, R. J. Noll, “Adaptive neural network in a hybrid optical/electronic architecture using lateral inhibition,” Appl. Opt. 28, 3852–3859 (1989).
    [CrossRef]
  20. C. A. Mead, Analog VLSI and Neural Systems (Addison-Wesley, Reading, Mass., 1989).
    [CrossRef]

1991

1990

1989

1986

L. A. Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C. Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, S. H. Lee, “Holographic optical interconnects for VLSI,” Opt. Eng. 25, 1109–1118 (1986).

1984

T. Ichioka, J. Tanida, “Optical parallel logic gates using a shadow-casting system for optical digital computers,” Proc. IEEE 72, 787–801 (1984).
[CrossRef]

1983

G. G. Gonclaves, H. J. De Man, “NORA: A racefree dynamic CMOS technique for pipelined logic structures,” IEEE J. Solid-State Circuits SC-18, 261–266 (1983).
[CrossRef]

1982

H. J. Krambeck, C. M. Lee, H. H. S. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits SC-17, 614–619 (1982).
[CrossRef]

Bergman, L. A.

L. A. Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C. Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, S. H. Lee, “Holographic optical interconnects for VLSI,” Opt. Eng. 25, 1109–1118 (1986).

Bristow, J.

de Groot, P. J.

De Man, H. J.

G. G. Gonclaves, H. J. De Man, “NORA: A racefree dynamic CMOS technique for pipelined logic structures,” IEEE J. Solid-State Circuits SC-18, 261–266 (1983).
[CrossRef]

Dickenson, A.

Drabik, T. J.

M. R. Feldman, C. G. Guest, T. J. Drabik, S. C. Esener, “Comparison between electrical and free-space optical interconnects for fine grain processor arrays based on interconnect density capabilities,” Appl. Opt. 28, 3820–3829 (1989).
[CrossRef] [PubMed]

L. A. Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C. Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, S. H. Lee, “Holographic optical interconnects for VLSI,” Opt. Eng. 25, 1109–1118 (1986).

T. J. Drabik, “Optically interconnected parallel processor arrays,” Ph.D dissertation (Georgia Institute of Technology, Atlanta, Ga., 1989), pp. 112–120.

Esener, S. C.

M. R. Feldman, C. G. Guest, T. J. Drabik, S. C. Esener, “Comparison between electrical and free-space optical interconnects for fine grain processor arrays based on interconnect density capabilities,” Appl. Opt. 28, 3820–3829 (1989).
[CrossRef] [PubMed]

L. A. Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C. Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, S. H. Lee, “Holographic optical interconnects for VLSI,” Opt. Eng. 25, 1109–1118 (1986).

Feldman, M.

L. A. Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C. Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, S. H. Lee, “Holographic optical interconnects for VLSI,” Opt. Eng. 25, 1109–1118 (1986).

Feldman, M. R.

Fukushima, S.

Gonclaves, G. G.

G. G. Gonclaves, H. J. De Man, “NORA: A racefree dynamic CMOS technique for pipelined logic structures,” IEEE J. Solid-State Circuits SC-18, 261–266 (1983).
[CrossRef]

Guest, C. C.

L. A. Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C. Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, S. H. Lee, “Holographic optical interconnects for VLSI,” Opt. Eng. 25, 1109–1118 (1986).

Guest, C. G.

Guha, A.

Hussain, A.

Ichioka, T.

T. Ichioka, J. Tanida, “Optical parallel logic gates using a shadow-casting system for optical digital computers,” Proc. IEEE 72, 787–801 (1984).
[CrossRef]

Ichioka, Y.

Itho, K.

Jannson, T.

Johnston, A. R.

L. A. Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C. Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, S. H. Lee, “Holographic optical interconnects for VLSI,” Opt. Eng. 25, 1109–1118 (1986).

Kobayashi, S.

Krambeck, H. J.

H. J. Krambeck, C. M. Lee, H. H. S. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits SC-17, 614–619 (1982).
[CrossRef]

Kurokawa, T.

Law, H. H. S.

H. J. Krambeck, C. M. Lee, H. H. S. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits SC-17, 614–619 (1982).
[CrossRef]

Lee, C. M.

H. J. Krambeck, C. M. Lee, H. H. S. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits SC-17, 614–619 (1982).
[CrossRef]

Lee, S. H.

L. A. Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C. Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, S. H. Lee, “Holographic optical interconnects for VLSI,” Opt. Eng. 25, 1109–1118 (1986).

Lee, S. S.

Lin, F.

MacDonald, R. I.

Matsumoto, T.

Mead, C. A.

C. A. Mead, Analog VLSI and Neural Systems (Addison-Wesley, Reading, Mass., 1989).
[CrossRef]

Neifeld, M. A.

Nixon, R.

L. A. Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C. Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, S. H. Lee, “Holographic optical interconnects for VLSI,” Opt. Eng. 25, 1109–1118 (1986).

Noguchi, K.

Noll, R. J.

Prise, M. E.

Psaltis, D.

Sakano, T.

Sayles, A. H.

A. H. Sayles, J. P. Uyemura, “An optoelectronic CMOS memory circuit for parallel detection and storage of optical data,” IEEE J. Solid-State Circuits 26, 1110–1115, (1991).
[CrossRef]

A. H. Sayles, “Design of integrated CMOS circuits for parallel detection and storage of optical data,” Ph.D. dissertation (Georgia Institute of Technology, Atlanta, Ga., 1990).

Strzelecki, E. M.

Sullivan, C.

Suzuki, H.

Tanida, J.

W. Zhang, K. Itho, J. Tanida, Y. Ichioka, “Hopfield model with multistage neurons and its optoelectronic implementation,” Appl. Opt. 30, 195–200 (1991).
[CrossRef] [PubMed]

T. Ichioka, J. Tanida, “Optical parallel logic gates using a shadow-casting system for optical digital computers,” Proc. IEEE 72, 787–801 (1984).
[CrossRef]

Uyemura, J. P.

A. H. Sayles, J. P. Uyemura, “An optoelectronic CMOS memory circuit for parallel detection and storage of optical data,” IEEE J. Solid-State Circuits 26, 1110–1115, (1991).
[CrossRef]

J. P. Uyemura, Fundamentals of MOS Digital Integrated Circuits (Addison-Wesley, Reading, Mass., 1988).

J. P. Uyemura, Circuit Design for CMOS VLSI (Kluwer Academic, Boston, Mass., 1992).
[CrossRef]

Wu, W. H.

L. A. Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C. Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, S. H. Lee, “Holographic optical interconnects for VLSI,” Opt. Eng. 25, 1109–1118 (1986).

Yamamura, A.

Yu, P.

L. A. Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C. Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, S. H. Lee, “Holographic optical interconnects for VLSI,” Opt. Eng. 25, 1109–1118 (1986).

Zhang, W.

Appl. Opt.

M. R. Feldman, C. G. Guest, T. J. Drabik, S. C. Esener, “Comparison between electrical and free-space optical interconnects for fine grain processor arrays based on interconnect density capabilities,” Appl. Opt. 28, 3820–3829 (1989).
[CrossRef] [PubMed]

P. J. de Groot, R. J. Noll, “Adaptive neural network in a hybrid optical/electronic architecture using lateral inhibition,” Appl. Opt. 28, 3852–3859 (1989).
[CrossRef]

A. Guha, J. Bristow, C. Sullivan, A. Hussain, “Optical interconnects for massively parallel architectures,” Appl. Opt. 29, 1077–1093 (1990).
[CrossRef] [PubMed]

T. Sakano, K. Noguchi, T. Matsumoto, “Optical limits for spatial interconnection networks using 2-D optical array devices,” Appl. Opt. 29, 1094–1100 (1990).
[CrossRef] [PubMed]

F. Lin, E. M. Strzelecki, T. Jannson, “Optical multiplanar VLSI interconnects based on multiplexed waveguide holograms,” Appl. Opt. 29, 1126–1133 (1990).
[CrossRef] [PubMed]

A. Dickenson, M. E. Prise, “Free-space optical interconnection scheme,” Appl. Opt. 29, 2001–2005 (1990).
[CrossRef]

D. Psaltis, M. A. Neifeld, A. Yamamura, S. Kobayashi, “Optical memory disks in optical information processing,” Appl. Opt. 29, 2038–2057 (1990).
[CrossRef] [PubMed]

S. Fukushima, T. Kurokawa, H. Suzuki, “Optical implementation of parallel digital adder and subtractor,” Appl. Opt. 29, 2099–2106 (1990).
[CrossRef] [PubMed]

W. Zhang, K. Itho, J. Tanida, Y. Ichioka, “Hopfield model with multistage neurons and its optoelectronic implementation,” Appl. Opt. 30, 195–200 (1991).
[CrossRef] [PubMed]

R. I. MacDonald, S. S. Lee, “Photodetector sensitivity control for weight-setting in optoelectronic neural networks,” Appl. Opt. 30, 176–179 (1991).
[CrossRef] [PubMed]

IEEE J. Solid-State Circuits

H. J. Krambeck, C. M. Lee, H. H. S. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits SC-17, 614–619 (1982).
[CrossRef]

G. G. Gonclaves, H. J. De Man, “NORA: A racefree dynamic CMOS technique for pipelined logic structures,” IEEE J. Solid-State Circuits SC-18, 261–266 (1983).
[CrossRef]

A. H. Sayles, J. P. Uyemura, “An optoelectronic CMOS memory circuit for parallel detection and storage of optical data,” IEEE J. Solid-State Circuits 26, 1110–1115, (1991).
[CrossRef]

Opt. Eng.

L. A. Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C. Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, S. H. Lee, “Holographic optical interconnects for VLSI,” Opt. Eng. 25, 1109–1118 (1986).

Proc. IEEE

T. Ichioka, J. Tanida, “Optical parallel logic gates using a shadow-casting system for optical digital computers,” Proc. IEEE 72, 787–801 (1984).
[CrossRef]

Other

C. A. Mead, Analog VLSI and Neural Systems (Addison-Wesley, Reading, Mass., 1989).
[CrossRef]

A. H. Sayles, “Design of integrated CMOS circuits for parallel detection and storage of optical data,” Ph.D. dissertation (Georgia Institute of Technology, Atlanta, Ga., 1990).

T. J. Drabik, “Optically interconnected parallel processor arrays,” Ph.D dissertation (Georgia Institute of Technology, Atlanta, Ga., 1989), pp. 112–120.

J. P. Uyemura, Fundamentals of MOS Digital Integrated Circuits (Addison-Wesley, Reading, Mass., 1988).

J. P. Uyemura, Circuit Design for CMOS VLSI (Kluwer Academic, Boston, Mass., 1992).
[CrossRef]

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Figures (12)

Fig. 1
Fig. 1

Hybrid optical–electronic logic. (a) Individual cell. (b) CMOS chip realization.

Fig. 2
Fig. 2

Photodiodes in a CMOS integrated circuit. (a) nMOS and pMOS cross-sectional view. (b) Integrated photodiode–MOSFET circuit symbol.

Fig. 3
Fig. 3

Detector circuits in CMOS. (a) pMOS pull-down. (b) nMOS current mirror.

Fig. 4
Fig. 4

Optically gated pass transistor logic. (a) nMOS circuit. (b) pMOS circuit. (c) CMOS TG circuit.

Fig. 5
Fig. 5

Hybrid optical–electronic CMOS logic circuits. (a) Three-input nor. (b) Two-input nand gate. (c) Proposed hybrid logic symbols.

Fig. 6
Fig. 6

Hybrid adder circuits. (a) Half-adder. (b) Hybrid 4-bit parallel adder.

Fig. 7
Fig. 7

Hybrid dynamic CMOS logic. (a) Inverter. (b) Three-input nor gate.

Fig. 8
Fig. 8

Series hybrid CMOS logic. (a) Two-input nand circuit. (b) Three-input and-or-invert logic gate.

Fig. 9
Fig. 9

Series-parallel dynamic logic gates. (a) Subfunction block definition. (b) Reversed subfunction grouping.

Fig. 10
Fig. 10

Optically loaded CMOS RAM array.

Fig. 11
Fig. 11

Spatial light modulator control using a hybrid CMOS array.

Fig. 12
Fig. 12

Optically reconfigured microprocessor system.

Equations (21)

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I L - I P = C 0 d V 0 d t ,
t ch ( R P op - I P ) V DD C 0 ,
Y = G A + G ¯ Y ( t - τ ) P ¯
X = G ¯ A + G [ X ( t - τ ) + P ] ,
F = C A + C ¯ [ F ( t - τ ) P ¯ n + P p ]
F 1 = P + A + B ¯ = P ¯ A ¯ B ¯ ,
F 2 = P 1 P 2 ¯ = P 1 ¯ + P 2 ¯ ;
F 1 = P i j P k l , F 2 = P i j + P k l , F 3 = P i j P k l , F 4 = P i j P k l ,
S 0 = A 0 P i j , C 0 = A 0 P i j ,
S n = A n P i j C n - 1 , C n = A n P i j + C n - 1 ( A n + P i j )
F A = ( A + P 1 ¯ ) = A ¯ P 1 ¯ ,
F B = A 1 + A 2 + A 3 + P 1 + P 2 + P 3 ¯ = ( A 1 + A 2 + A 3 ) ¯ ( P 1 + P 2 + P 3 ) ¯ ,
F K = ( i = 1 K A i ¯ ) ( i = 1 K P i ¯ )
F S = P 1 + A 1 P 2 + A 1 A 2 ¯ = ( P 1 + A 1 P 2 ) ¯ ( A 1 A 2 ) ¯ .
F K S = ( P 1 + A 1 P 2 + A 1 A 2 P 3 + + A 1 A 2 A K - 1 P K ¯ ) × ( A 1 A 2 A 3 A K ¯ ) ,
F C 1 = ( P 1 + P 3 + A 3 + A 1 P 2 + A 1 A 2 ¯ ) = G 1 ¯ G 2 ¯ ,
F a = P 1 + P 2 + ( A 1 + A 2 ) ( A 3 + P 3 ) ¯ , F b = P 1 + A 1 ( A 2 + A 3 + P 2 + P 3 ) ¯ ,
G i = k A i k + k P i k = G i e + G i p .
F = G 1 p + G 1 e G 2 ¯ .
F C 2 = G 1 p + G 1 e ( G 2 p + G 2 e { G 3 p + G 3 e [ + G K - 1 e ( G K ) ] } ) . ¯
F i j = P i j R i j ,

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