Abstract

We describe the design and implementation of a bit-serial, four-bit, binary optical counter. The counter was designed and simulated using a digital optical simulation program developed for this purpose. It consists of five switches, a 4-bit fiber loop memory to store the count, four splitters, and fibers to interconnect the components. The counter is presently limited to a clock rate of 50 MHz because of the propagation delay in the single-bit time feedback loop. As designed, the same hardware may be used to count any even number of bits simply by changing the lengths of two fiber loops. The counter is unique in that it does not employ latches or other synchronizing memory elements, rather relying on a time-of-flight architecture. We describe the system issues involved in construction of the counter as well as the novel requirements on the switch drive electronics. We then outline the issues still to be addressed for the current counter and conclude with suggested design alternatives to improve its operation and increase its clock rate.

© 1991 Optical Society of America

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