Abstract

This paper presents a case study in the design and analysis of a massively parallel optical computer, SPARO, a novel scalable computer intended for symbolic and numeric computing. SPARO was designed for fine-grained parallel processing of combinator graph reduction, a special case of the graph reduction computational model, found most appropriate for parallel optical processing in earlier studies. The architecture consists of a planar array of optical processors that communicate through simple messages (data packets) over an optical interconnection network. A technique called instruction passing is used to realize distributed control of the architecture. Instruction passing can also be used to implement complex structures such as recursion and iteration. Each individual processor in SPARO is a finite state machine that is implemented using symbolic substitution techniques, while gateable interconnects are used to realize data movements between the processors and network. Performance analysis of SPARO reveals that while discrete computing structures can be implemented using optical techniques, massively parallel optical architectures for traditional computational models are currently unable to compete with electronic ones due to the lack of large scale addressable optical memory devices and large scale integratable optical computing elements. However, optical interconnections appear very promising for providing the network throughput necessary for these parallel architectures.

© 1990 Optical Society of America

Optical interconnections for massively parallel architectures

Aloke Guha, Julian Bristow, Charles Sullivan, and Anis Husain
Appl. Opt. 29(8) 1077-1093 (1990)

Scalable optical hypercube-based interconnection network for massively parallel computing

Ahmed Louri and Hongki Sung
Appl. Opt. 33(32) 7588-7598 (1994)

Optical binary de Bruijn networks for massively parallel computing: design methodology and feasibility study

Ahmed Louri and Hongki Sung
Appl. Opt. 34(29) 6714-6722 (1995)

Optical content-addressable parallel processor: architecture, algorithms, and design concepts

Ahmed Louri
Appl. Opt. 31(17) 3241-3258 (1992)

Parallel algorithms based on expander graphs for optical computing

Ramamohan Paturi, Dau-Tsuong Lu, Joseph E. Ford, Sadik C. Esener, and Sing H. Lee
Appl. Opt. 30(8) 917-927 (1991)