Abstract

The crossover network is a multistage interconnection network that shows potential for use in optical computing and photonic switching applications. In this paper, a proof of topological equivalence between the crossover network and the modified data manipulator network is presented. It is shown that the Gray Code can be used as the mapping function between the crossover network and a network which is equivalent to the modified data manipulator network. Given the results of this proof, the optical crossover network can then be proposed as the optical interconnection fabric for many switching and computing applications.

© 1989 Optical Society of America

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References

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  1. D. S. Wise, “Compact Layouts of Banyan/FFT Networks,” in VLSI Systems and Computation, H. T. Kung, B. Sproull, G. Steele, Eds., (Computer Science, Rockville, Md, 1981).
    [Crossref]
  2. J. Jahns, M. J. Murdocca, “Crossover Networks and Their Optical Implementation,” Appl. Opt. 27, 3155–3160 (1988).
    [Crossref] [PubMed]
  3. T.-Y. Feng, “Data Manipulating Functions in Parallel Processors and Their Implementations,” IEEE Trans. Comput. C-023, 309–000 (1974).
    [Crossref]
  4. C.-L. Wu, T.-Y. Feng, “on a Class of Multistage Interconnection Networks,” IEEE Trans. Comput. C-29, 694–000 (1980).
    [Crossref]
  5. H. S. Stone, “Parallel Processing with the Perfect Shuffle,” IEEE Trans. Comput. C-20, 153–000 (1971).
    [Crossref]
  6. L. L. Goke, A. Lipovski, “Banyan Networks for Partitioning Multiprocessing Systems,” in Proceedings of the First Annual Computer Architecture Conference (IEEE, Piscataway, N.J., 1973).
  7. D. K. Lawrie, “Access and Alignment of Data in an Array Processor,” IEEE Trans. Comput. C-24, 1145–000 (1975).
    [Crossref]
  8. K. E. Batcher, “The Flip Network in staran,” in Proceedings of the 1976 International Conference on Parallel Processing (IEEE, Piscataway, N.J., 1976).
  9. H. J. Siegel, “Analysis Techniques for SIMD Machine Interconnection Networks and the Effects of Processor Address Masks,” IEEE Trans. Comput. C-26, 153–000 (1977).
    [Crossref]
  10. M. C. Pease, “The Indirect Binary n-cube Microprocessor Array,” IEEE Trans. Comput. C-26, 458–000 (1977).
    [Crossref]

1988 (1)

1980 (1)

C.-L. Wu, T.-Y. Feng, “on a Class of Multistage Interconnection Networks,” IEEE Trans. Comput. C-29, 694–000 (1980).
[Crossref]

1977 (2)

H. J. Siegel, “Analysis Techniques for SIMD Machine Interconnection Networks and the Effects of Processor Address Masks,” IEEE Trans. Comput. C-26, 153–000 (1977).
[Crossref]

M. C. Pease, “The Indirect Binary n-cube Microprocessor Array,” IEEE Trans. Comput. C-26, 458–000 (1977).
[Crossref]

1975 (1)

D. K. Lawrie, “Access and Alignment of Data in an Array Processor,” IEEE Trans. Comput. C-24, 1145–000 (1975).
[Crossref]

1974 (1)

T.-Y. Feng, “Data Manipulating Functions in Parallel Processors and Their Implementations,” IEEE Trans. Comput. C-023, 309–000 (1974).
[Crossref]

1971 (1)

H. S. Stone, “Parallel Processing with the Perfect Shuffle,” IEEE Trans. Comput. C-20, 153–000 (1971).
[Crossref]

Batcher, K. E.

K. E. Batcher, “The Flip Network in staran,” in Proceedings of the 1976 International Conference on Parallel Processing (IEEE, Piscataway, N.J., 1976).

Feng, T.-Y.

C.-L. Wu, T.-Y. Feng, “on a Class of Multistage Interconnection Networks,” IEEE Trans. Comput. C-29, 694–000 (1980).
[Crossref]

T.-Y. Feng, “Data Manipulating Functions in Parallel Processors and Their Implementations,” IEEE Trans. Comput. C-023, 309–000 (1974).
[Crossref]

Goke, L. L.

L. L. Goke, A. Lipovski, “Banyan Networks for Partitioning Multiprocessing Systems,” in Proceedings of the First Annual Computer Architecture Conference (IEEE, Piscataway, N.J., 1973).

Jahns, J.

Lawrie, D. K.

D. K. Lawrie, “Access and Alignment of Data in an Array Processor,” IEEE Trans. Comput. C-24, 1145–000 (1975).
[Crossref]

Lipovski, A.

L. L. Goke, A. Lipovski, “Banyan Networks for Partitioning Multiprocessing Systems,” in Proceedings of the First Annual Computer Architecture Conference (IEEE, Piscataway, N.J., 1973).

Murdocca, M. J.

Pease, M. C.

M. C. Pease, “The Indirect Binary n-cube Microprocessor Array,” IEEE Trans. Comput. C-26, 458–000 (1977).
[Crossref]

Siegel, H. J.

H. J. Siegel, “Analysis Techniques for SIMD Machine Interconnection Networks and the Effects of Processor Address Masks,” IEEE Trans. Comput. C-26, 153–000 (1977).
[Crossref]

Stone, H. S.

H. S. Stone, “Parallel Processing with the Perfect Shuffle,” IEEE Trans. Comput. C-20, 153–000 (1971).
[Crossref]

Wise, D. S.

D. S. Wise, “Compact Layouts of Banyan/FFT Networks,” in VLSI Systems and Computation, H. T. Kung, B. Sproull, G. Steele, Eds., (Computer Science, Rockville, Md, 1981).
[Crossref]

Wu, C.-L.

C.-L. Wu, T.-Y. Feng, “on a Class of Multistage Interconnection Networks,” IEEE Trans. Comput. C-29, 694–000 (1980).
[Crossref]

Appl. Opt. (1)

IEEE Trans. Comput. (6)

T.-Y. Feng, “Data Manipulating Functions in Parallel Processors and Their Implementations,” IEEE Trans. Comput. C-023, 309–000 (1974).
[Crossref]

C.-L. Wu, T.-Y. Feng, “on a Class of Multistage Interconnection Networks,” IEEE Trans. Comput. C-29, 694–000 (1980).
[Crossref]

H. S. Stone, “Parallel Processing with the Perfect Shuffle,” IEEE Trans. Comput. C-20, 153–000 (1971).
[Crossref]

D. K. Lawrie, “Access and Alignment of Data in an Array Processor,” IEEE Trans. Comput. C-24, 1145–000 (1975).
[Crossref]

H. J. Siegel, “Analysis Techniques for SIMD Machine Interconnection Networks and the Effects of Processor Address Masks,” IEEE Trans. Comput. C-26, 153–000 (1977).
[Crossref]

M. C. Pease, “The Indirect Binary n-cube Microprocessor Array,” IEEE Trans. Comput. C-26, 458–000 (1977).
[Crossref]

Other (3)

K. E. Batcher, “The Flip Network in staran,” in Proceedings of the 1976 International Conference on Parallel Processing (IEEE, Piscataway, N.J., 1976).

L. L. Goke, A. Lipovski, “Banyan Networks for Partitioning Multiprocessing Systems,” in Proceedings of the First Annual Computer Architecture Conference (IEEE, Piscataway, N.J., 1973).

D. S. Wise, “Compact Layouts of Banyan/FFT Networks,” in VLSI Systems and Computation, H. T. Kung, B. Sproull, G. Steele, Eds., (Computer Science, Rockville, Md, 1981).
[Crossref]

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Figures (4)

Fig. 1
Fig. 1

Crossover network (nodes and links labeled with physical addresses).

Fig. 2
Fig. 2

Hardware required for optical implementation of crossover network.

Fig. 3
Fig. 3

Modified data manipulator network (nodes and links labeled with physical addresses).

Fig. 4
Fig. 4

Crossover network (nodes and links labeled with logical addresses).

Equations (17)

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( b l , b l 1 , , b 1 ) = γ i [ ( p l , p l 1 , , p 1 ) ] , = Gray code [ ( p l , p l 1 , , P 1 ) ] = ( p l , p l X O R p l 1 , , p 3 X O R p 2 , p 2 X O R p 1 ) ,
A X O R B = ( A A N D B ¯ ) O R ( A ¯ A N D B ) .
( p l , p l 1 , , p 1 ) = γ i 1 [ ( b l b l 1 , , b 1 ) ] = [ b l , b l X O R b l 1 , b l X O R b l 1 X O R b l 2 , , × b l X O R b l 1 b 2 X O R b 1 ) ] .
β i 0 [ p l p l 1 , , p 1 ) i ] = ( p l p l 1 , , p 1 ) i + 1 .
β i 1 [ ( p l p l 1 , , p 1 ) i ] = ( p l , p l 1 , , p l i + 1 , p l i ¯ , p l i 1 , , p 1 ) i + 1 .
α i 0 [ ( p l , p l 1 , , p 1 ) ] = ( p l , p l 1 , , p 1 ) i + 1 .
α i 1 [ ( p l p l 1 , , p 1 ) i ] = ( p l , p l 1 , , p l i + 1 , p l i ¯ , p l i 1 ¯ , , p 1 ¯ ) i + 1 .
β i 0 { γ i [ ( p l , p l 1 , , p 1 ) ] } = γ i + 1 { α i 0 [ ( p l , p l 1 , , p 1 ) i ] } ,
β i 1 { γ i [ ( p l , p l 1 , , p 1 ) 1 ] } = γ i + 1 { α i 1 [ ( p l , p l 1 , , p 1 ) i ] } .
β i 0 { γ i [ ( p l , p l 1 , , p 1 ) } = γ i + 1 { α i 0 [ ( p l , p l 1 , , p 1 ) } ,
β i 0 [ ( p l , p l X O R p l 1 , , p 2 X O R p 1 ) i ] = γ i + 1 [ ( p l , p l 1 , , p 1 ) i + 1 ] ,
( p l , p l X O R p l 1 , , p 2 X O R p 1 ) i + 1 = ( p l , p l X O R p l 1 , , p 2 X O R p 1 ) i + 1 .
β i 1 { γ i [ ( p l , p l 1 , , p 1 ) i ] } = γ i + 1 [ α i 1 { ( p l , p l 1 , , p 1 ) i ] } ,
β i 1 [ ( p l , p l X O R p l 1 , , p 2 X O R p 1 ) ] = γ i + 1 [ ( p l , , p l i + 1 , p l i ¯ , p l i 1 ¯ , , p 1 ¯ ) i + 1 ] ,
( p l , p l X O R p l 1 , , p l i + 2 X O R p l i + 1 , p l i + 1 X O R p l i ¯ , p l i X O R p l i 1 , , p 2 X O R p 1 ) i + 1 = ( p l , p l X O R p l 1 , p l i + 2 X O R p l i + 1 , p l i + 1 X O R p l i , p l i ¯ X O R p l i 1 ¯ , , p 2 ¯ X O R p 1 ¯ ) i + 1 .
( p l , p l X O R p l 1 , , p l i + 2 X O R p l i + 1 , p l i + 1 X O R p l i ¯ , p l i X O R p l i 1 , , p 2 X O R p 1 ) i + 1 = ( p l , p l X O R p l 1 , , p l i + 2 X O R p l i + 1 , p l i + 1 X O R p l i ¯ , p l i X O R p l i 1 , , p 2 X O R p 1 ) i + 1 .
( p l , p l X O R P l 1 , , p l i + 2 X O R p l i + 1 , p l i + 1 X O R p l i ¯ , p l i X O R P l i 1 , , p 2 X O R p 1 ) i + 1 = ( p l , p l X O R P l 1 , , p l i + 2 X O R p l i , p l i + 1 X O R p l i ¯ , p l i X O R p l i 1 , , p 2 X O R p 1 ) i + 1 .

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