Abstract

While the advantages of optical over electrical interconnects for conventional 2-D VLSI and wafer-scale-integrated (WSI) circuits have not been clearly demonstrated, for 3-D interconnection structures such as those necessary for stacked wafer and similar architectures, the trade-off between using optical or electrical methods for vertical links is not straightforward. Current work on fabricating a through-wafer optical interconnect within a hybrid-WSI environment is motivated by the need to obtain experimental data on the overall performance of an optical interconnect so that this trade-off can be clarified in the case of hybrid-WSI and in the general case at least more well defined. This paper details the design and fabrication of SiO2 Fresnel phase plate lens arrays for use in the experimental 1.3-μm wavelength through-wafer optical interconnects to be constructed. These 0.8-N.A. lenses have submicron minimum linewidths and are VLSI process compatible. Preliminary results are presented indicating that, with the use of these lens arrays, vertical optical interconnect densities comparable with that of on chip bonding pads (≈250-μm pitch) are obtainable within these architectures.

© 1987 Optical Society of America

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References

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  1. P. R. Haugen, S. Rychnovsky, A. Husain, L. D. Hutcheson, “Optical Interconnects for High Speed Computing,” Opt. Eng. 25, 1076 (1986).
    [CrossRef]
  2. C. M. Lin, D. L. Carter, “Photonic I/O's at the PWB and Chip Level?,” at Sixth International Electronics and Packaging Conference, San Diego (16–20 Nov.1986).
  3. R. K. Kostuk, J. W. Goodman, L. Hesselink, “Optical Imaging Applied to Microelectronic Chip-to-Chip Interconnections,” Appl. Opt. 24, 2851 (1985).
    [CrossRef] [PubMed]
  4. M. Hatamian, G. Cash, “A 70MHz 8 bit × 8 bit Parallel Pipelined Multiplier in 2.5μm CMOS,” IEEE J. Solid-State Circuits SC-21, 505 (Aug.1986).
    [CrossRef]
  5. L. A. Hornak, S. K. Tewksbury, “On the Feasibility of Through-Wafer Optical Interconnects for Hybrid Wafer-Scale-Integrated Architectures,” IEEE Trans. Electron Devices ED-34, 1557 (1987).
    [CrossRef]
  6. S. K. Tewksbury, L. A. Hornak, A. Ligtenberg, “The Impact of Component Interconnects on Future Large Scale Systems,” Proc IEEE (in revision).
  7. J. Grinberg, R. G. R. Nudd, R. D. Etchells, “A Cellular VLSI Architecture,” Computer69 (Jan.1984).
    [CrossRef]
  8. G-I. Hatakoshi, K. Goto, “Grating Lenses for the Semiconductor Laser Wavelength,” Appl. Opt. 24, 4307 (1985).
    [CrossRef] [PubMed]
  9. W. S. Chang, P. R. Ashley, “Fresnel Lenses in Optical Waveguides,” IEEE J. Quantum Electron. QE-16, 744 (1980).
    [CrossRef]
  10. R. Magnusson, T. K. Gaylord, “Diffraction Efficiencies of Thin Phase Gratings with Arbitrary Grating Shape,” J. Opt. Soc. Am. 68, 806 (1978).
    [CrossRef]
  11. S. K. Tewksbury, T. L. Lindstrom, L. A. Hornak, M. R. Biazzo, R. H. Bosworth, “Chip Alignment Templates for Multi-Chip Module Assembly,” IEEE Trans. Comput. Hybrid Manuf. Technol. CHMT-10, 111 (Mar.1987).
    [CrossRef]
  12. P. P. Deimel et al., “Individually Addressable Monolithic 1×12 Light-Emitting Diode Array,” IEEE IOSA J. Lightwave Technol. LT-3, 988 (1985).
    [CrossRef]
  13. M. G. Brown et al., “Fully Optically and Electrically Interfaced, Monolithic 1×12 Array of In0.53Ga0.47As/InP p-i-n Photodiodes,” International Electron Devices Meeting, p. 727 (1984).
  14. C. J. Smith, Optics (Edward Arnold, Ltd.Baltimore, 1960), pp. 567–77.

1987 (2)

L. A. Hornak, S. K. Tewksbury, “On the Feasibility of Through-Wafer Optical Interconnects for Hybrid Wafer-Scale-Integrated Architectures,” IEEE Trans. Electron Devices ED-34, 1557 (1987).
[CrossRef]

S. K. Tewksbury, T. L. Lindstrom, L. A. Hornak, M. R. Biazzo, R. H. Bosworth, “Chip Alignment Templates for Multi-Chip Module Assembly,” IEEE Trans. Comput. Hybrid Manuf. Technol. CHMT-10, 111 (Mar.1987).
[CrossRef]

1986 (2)

P. R. Haugen, S. Rychnovsky, A. Husain, L. D. Hutcheson, “Optical Interconnects for High Speed Computing,” Opt. Eng. 25, 1076 (1986).
[CrossRef]

M. Hatamian, G. Cash, “A 70MHz 8 bit × 8 bit Parallel Pipelined Multiplier in 2.5μm CMOS,” IEEE J. Solid-State Circuits SC-21, 505 (Aug.1986).
[CrossRef]

1985 (3)

1984 (2)

M. G. Brown et al., “Fully Optically and Electrically Interfaced, Monolithic 1×12 Array of In0.53Ga0.47As/InP p-i-n Photodiodes,” International Electron Devices Meeting, p. 727 (1984).

J. Grinberg, R. G. R. Nudd, R. D. Etchells, “A Cellular VLSI Architecture,” Computer69 (Jan.1984).
[CrossRef]

1980 (1)

W. S. Chang, P. R. Ashley, “Fresnel Lenses in Optical Waveguides,” IEEE J. Quantum Electron. QE-16, 744 (1980).
[CrossRef]

1978 (1)

Ashley, P. R.

W. S. Chang, P. R. Ashley, “Fresnel Lenses in Optical Waveguides,” IEEE J. Quantum Electron. QE-16, 744 (1980).
[CrossRef]

Biazzo, M. R.

S. K. Tewksbury, T. L. Lindstrom, L. A. Hornak, M. R. Biazzo, R. H. Bosworth, “Chip Alignment Templates for Multi-Chip Module Assembly,” IEEE Trans. Comput. Hybrid Manuf. Technol. CHMT-10, 111 (Mar.1987).
[CrossRef]

Bosworth, R. H.

S. K. Tewksbury, T. L. Lindstrom, L. A. Hornak, M. R. Biazzo, R. H. Bosworth, “Chip Alignment Templates for Multi-Chip Module Assembly,” IEEE Trans. Comput. Hybrid Manuf. Technol. CHMT-10, 111 (Mar.1987).
[CrossRef]

Brown, M. G.

M. G. Brown et al., “Fully Optically and Electrically Interfaced, Monolithic 1×12 Array of In0.53Ga0.47As/InP p-i-n Photodiodes,” International Electron Devices Meeting, p. 727 (1984).

Carter, D. L.

C. M. Lin, D. L. Carter, “Photonic I/O's at the PWB and Chip Level?,” at Sixth International Electronics and Packaging Conference, San Diego (16–20 Nov.1986).

Cash, G.

M. Hatamian, G. Cash, “A 70MHz 8 bit × 8 bit Parallel Pipelined Multiplier in 2.5μm CMOS,” IEEE J. Solid-State Circuits SC-21, 505 (Aug.1986).
[CrossRef]

Chang, W. S.

W. S. Chang, P. R. Ashley, “Fresnel Lenses in Optical Waveguides,” IEEE J. Quantum Electron. QE-16, 744 (1980).
[CrossRef]

Deimel, P. P.

P. P. Deimel et al., “Individually Addressable Monolithic 1×12 Light-Emitting Diode Array,” IEEE IOSA J. Lightwave Technol. LT-3, 988 (1985).
[CrossRef]

Etchells, R. D.

J. Grinberg, R. G. R. Nudd, R. D. Etchells, “A Cellular VLSI Architecture,” Computer69 (Jan.1984).
[CrossRef]

Gaylord, T. K.

Goodman, J. W.

Goto, K.

Grinberg, J.

J. Grinberg, R. G. R. Nudd, R. D. Etchells, “A Cellular VLSI Architecture,” Computer69 (Jan.1984).
[CrossRef]

Hatakoshi, G-I.

Hatamian, M.

M. Hatamian, G. Cash, “A 70MHz 8 bit × 8 bit Parallel Pipelined Multiplier in 2.5μm CMOS,” IEEE J. Solid-State Circuits SC-21, 505 (Aug.1986).
[CrossRef]

Haugen, P. R.

P. R. Haugen, S. Rychnovsky, A. Husain, L. D. Hutcheson, “Optical Interconnects for High Speed Computing,” Opt. Eng. 25, 1076 (1986).
[CrossRef]

Hesselink, L.

Hornak, L. A.

L. A. Hornak, S. K. Tewksbury, “On the Feasibility of Through-Wafer Optical Interconnects for Hybrid Wafer-Scale-Integrated Architectures,” IEEE Trans. Electron Devices ED-34, 1557 (1987).
[CrossRef]

S. K. Tewksbury, T. L. Lindstrom, L. A. Hornak, M. R. Biazzo, R. H. Bosworth, “Chip Alignment Templates for Multi-Chip Module Assembly,” IEEE Trans. Comput. Hybrid Manuf. Technol. CHMT-10, 111 (Mar.1987).
[CrossRef]

S. K. Tewksbury, L. A. Hornak, A. Ligtenberg, “The Impact of Component Interconnects on Future Large Scale Systems,” Proc IEEE (in revision).

Husain, A.

P. R. Haugen, S. Rychnovsky, A. Husain, L. D. Hutcheson, “Optical Interconnects for High Speed Computing,” Opt. Eng. 25, 1076 (1986).
[CrossRef]

Hutcheson, L. D.

P. R. Haugen, S. Rychnovsky, A. Husain, L. D. Hutcheson, “Optical Interconnects for High Speed Computing,” Opt. Eng. 25, 1076 (1986).
[CrossRef]

Kostuk, R. K.

Ligtenberg, A.

S. K. Tewksbury, L. A. Hornak, A. Ligtenberg, “The Impact of Component Interconnects on Future Large Scale Systems,” Proc IEEE (in revision).

Lin, C. M.

C. M. Lin, D. L. Carter, “Photonic I/O's at the PWB and Chip Level?,” at Sixth International Electronics and Packaging Conference, San Diego (16–20 Nov.1986).

Lindstrom, T. L.

S. K. Tewksbury, T. L. Lindstrom, L. A. Hornak, M. R. Biazzo, R. H. Bosworth, “Chip Alignment Templates for Multi-Chip Module Assembly,” IEEE Trans. Comput. Hybrid Manuf. Technol. CHMT-10, 111 (Mar.1987).
[CrossRef]

Magnusson, R.

Nudd, R. G. R.

J. Grinberg, R. G. R. Nudd, R. D. Etchells, “A Cellular VLSI Architecture,” Computer69 (Jan.1984).
[CrossRef]

Rychnovsky, S.

P. R. Haugen, S. Rychnovsky, A. Husain, L. D. Hutcheson, “Optical Interconnects for High Speed Computing,” Opt. Eng. 25, 1076 (1986).
[CrossRef]

Smith, C. J.

C. J. Smith, Optics (Edward Arnold, Ltd.Baltimore, 1960), pp. 567–77.

Tewksbury, S. K.

S. K. Tewksbury, T. L. Lindstrom, L. A. Hornak, M. R. Biazzo, R. H. Bosworth, “Chip Alignment Templates for Multi-Chip Module Assembly,” IEEE Trans. Comput. Hybrid Manuf. Technol. CHMT-10, 111 (Mar.1987).
[CrossRef]

L. A. Hornak, S. K. Tewksbury, “On the Feasibility of Through-Wafer Optical Interconnects for Hybrid Wafer-Scale-Integrated Architectures,” IEEE Trans. Electron Devices ED-34, 1557 (1987).
[CrossRef]

S. K. Tewksbury, L. A. Hornak, A. Ligtenberg, “The Impact of Component Interconnects on Future Large Scale Systems,” Proc IEEE (in revision).

Appl. Opt. (2)

Computer (1)

J. Grinberg, R. G. R. Nudd, R. D. Etchells, “A Cellular VLSI Architecture,” Computer69 (Jan.1984).
[CrossRef]

IEEE IOSA J. Lightwave Technol. (1)

P. P. Deimel et al., “Individually Addressable Monolithic 1×12 Light-Emitting Diode Array,” IEEE IOSA J. Lightwave Technol. LT-3, 988 (1985).
[CrossRef]

IEEE J. Quantum Electron. (1)

W. S. Chang, P. R. Ashley, “Fresnel Lenses in Optical Waveguides,” IEEE J. Quantum Electron. QE-16, 744 (1980).
[CrossRef]

IEEE J. Solid-State Circuits (1)

M. Hatamian, G. Cash, “A 70MHz 8 bit × 8 bit Parallel Pipelined Multiplier in 2.5μm CMOS,” IEEE J. Solid-State Circuits SC-21, 505 (Aug.1986).
[CrossRef]

IEEE Trans. Comput. Hybrid Manuf. Technol. (1)

S. K. Tewksbury, T. L. Lindstrom, L. A. Hornak, M. R. Biazzo, R. H. Bosworth, “Chip Alignment Templates for Multi-Chip Module Assembly,” IEEE Trans. Comput. Hybrid Manuf. Technol. CHMT-10, 111 (Mar.1987).
[CrossRef]

IEEE Trans. Electron Devices (1)

L. A. Hornak, S. K. Tewksbury, “On the Feasibility of Through-Wafer Optical Interconnects for Hybrid Wafer-Scale-Integrated Architectures,” IEEE Trans. Electron Devices ED-34, 1557 (1987).
[CrossRef]

International Electron Devices Meeting (1)

M. G. Brown et al., “Fully Optically and Electrically Interfaced, Monolithic 1×12 Array of In0.53Ga0.47As/InP p-i-n Photodiodes,” International Electron Devices Meeting, p. 727 (1984).

J. Opt. Soc. Am. (1)

Opt. Eng. (1)

P. R. Haugen, S. Rychnovsky, A. Husain, L. D. Hutcheson, “Optical Interconnects for High Speed Computing,” Opt. Eng. 25, 1076 (1986).
[CrossRef]

Other (3)

C. M. Lin, D. L. Carter, “Photonic I/O's at the PWB and Chip Level?,” at Sixth International Electronics and Packaging Conference, San Diego (16–20 Nov.1986).

S. K. Tewksbury, L. A. Hornak, A. Ligtenberg, “The Impact of Component Interconnects on Future Large Scale Systems,” Proc IEEE (in revision).

C. J. Smith, Optics (Edward Arnold, Ltd.Baltimore, 1960), pp. 567–77.

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Figures (13)

Fig. 1
Fig. 1

Example of a stacked wafer H-WSI architecture.

Fig. 2
Fig. 2

Example H-WSI architecture showing a through-wafer optical interconnect array.

Fig. 3
Fig. 3

Experimental setup used to simulate the behavior of Fresnel phase plate lenses in the architecture of Fig. 1.

Fig. 4
Fig. 4

Transmission medium for the design of the experimental phase plates.

Fig. 5
Fig. 5

Diagram of a phase plate lens and the rays used in the lens equation derivation.

Fig. 6
Fig. 6

Ray diagram used in determining the approximate change in the source distance as a result of the small LED array-lens wafer gap.

Fig. 7
Fig. 7

Final mask showing (a) a full phase plate lens pattern and (b) a corner region of 0.5-μm zones. Light regions are chrome. Secondary patterns in (a) are from screen printing.

Fig. 8
Fig. 8

Initial fabrication results showing (a) a completed 1 × 6 array of SiO2 phase plates on 250-μm centers and (b) the center zones of one lens.

Fig. 9
Fig. 9

Phase plate patterned in 2-μm thick resist. The marker length in (b) represents 1-μm.

Fig. 10
Fig. 10

Completed phase plate fabricated with the 2-μm lithographic process showing the (a) center and (b) 0.75-μm edge zones. Marker length is 1 μm.

Fig. 11
Fig. 11

Experimental setup used for measuring the intensity distribution a distance i from the lens when the LED array is a distance z from the lens wafer back.

Fig. 12
Fig. 12

Image intensity distributions behind the lens of a single LED at a position z under the lens wafer. The three values of i are the image distances behind the lenses for three different positions z of the LED array. Each grid side represents 3.0 μm.

Fig. 13
Fig. 13

Intensity distribution of the image when the LED array is ≈1 mm from the lens wafer. Crosstalk of the single LED into the neighboring lens begins to appear.

Equations (9)

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r k 2 = k f λ 0 n ,
r k 2 = k f 1 λ 0 n 1 .
n 2 X 2 2 + k f 1 λ 0 n 1 + n 1 X 1 2 + k f 1 λ 0 n 1 n 2 X 2 n 1 X 1 = k λ 0 2 .
f 1 k λ 0 n 1 n 1 X 1 + f 1 k λ 0 n 2 n 1 X 2 = k λ 0
1 X 1 + n 2 X 2 n 1 = 1 f 1 .
r k 2 = k λ 0 n 1 ( 1 X 1 + n 2 X 2 n 1 ) 1 .
θ 1 = tan 1 h z + t ,
θ 2 = sin 1 ( n 1 n 2 sin θ 1 ) .
d = z tan θ 1 tan θ 2 .

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