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  1. C. M. Verberg, R. P. Kenan, H. J. Caulfield, J. E. Ludman, P. D. Stilwell, Appl. Opt. 23 (15Mar.1984).
  2. E. V. Krishnamurthy, IEEE Trans. Comput. COM-20, 470 (1971).
    [CrossRef]

1984 (1)

C. M. Verberg, R. P. Kenan, H. J. Caulfield, J. E. Ludman, P. D. Stilwell, Appl. Opt. 23 (15Mar.1984).

1971 (1)

E. V. Krishnamurthy, IEEE Trans. Comput. COM-20, 470 (1971).
[CrossRef]

Caulfield, H. J.

C. M. Verberg, R. P. Kenan, H. J. Caulfield, J. E. Ludman, P. D. Stilwell, Appl. Opt. 23 (15Mar.1984).

Kenan, R. P.

C. M. Verberg, R. P. Kenan, H. J. Caulfield, J. E. Ludman, P. D. Stilwell, Appl. Opt. 23 (15Mar.1984).

Krishnamurthy, E. V.

E. V. Krishnamurthy, IEEE Trans. Comput. COM-20, 470 (1971).
[CrossRef]

Ludman, J. E.

C. M. Verberg, R. P. Kenan, H. J. Caulfield, J. E. Ludman, P. D. Stilwell, Appl. Opt. 23 (15Mar.1984).

Stilwell, P. D.

C. M. Verberg, R. P. Kenan, H. J. Caulfield, J. E. Ludman, P. D. Stilwell, Appl. Opt. 23 (15Mar.1984).

Verberg, C. M.

C. M. Verberg, R. P. Kenan, H. J. Caulfield, J. E. Ludman, P. D. Stilwell, Appl. Opt. 23 (15Mar.1984).

Appl. Opt. (1)

C. M. Verberg, R. P. Kenan, H. J. Caulfield, J. E. Ludman, P. D. Stilwell, Appl. Opt. 23 (15Mar.1984).

IEEE Trans. Comput. (1)

E. V. Krishnamurthy, IEEE Trans. Comput. COM-20, 470 (1971).
[CrossRef]

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Figures (4)

Fig. 1
Fig. 1

Basic unit of an optical pipeline polynomial computer receives data a1 from the left, b1 from above, x0 from below and sends the result a1x0 + b1 to the right as shown in (a). Immediately after that the module is ready to receive new data, e.g., a0,x1,0, to calculate a new result. The data flow is shown in (b).

Fig. 2
Fig. 2

Data flow for ax = b for 2-bit accuracy. Note all a values are addressed in parallel to the appropriate ax multiplier. The x values move downward one multiplier each clock period. The b values are added when all the ax terms for the corresponding power of 2 have been calculated. The sum over five time periods gives the proper dk values for ax + b = d = d424 + d323 + … + d0.

Fig. 3
Fig. 3

With N + 1 multipliers we can time share the channel. Thus the first channel can calculate the 20 coefficient and then the 23 coefficient. The data flow pattern is again obvious, and again one power of 2 is completed each clock time.

Fig. 4
Fig. 4

Possible data flow pattern for a single processor.

Equations (18)

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The single pipeline module performs a x + b = d .
a = a 0 2 0 + a 1 2 1 + + a N 2 N ,
x = x 0 2 0 + x 1 2 1 + x N 2 N ,
b = b 2 2 0 + b 1 2 1 + b B 2 N .
y = x / b .
P ( x ) k = 0 n a k b k y k = k = 0 n W k y k .
z = 1 / y = b / x .
P ( x ) k = 0 n a k b k z - k = z - n ( k = 0 n a k b k z n - k ) = z - n k = 0 n W k z n - k .
P 1 ( x ) = k = 0 n W k X k
P 2 ( x ) = k = 0 n W k z n - k
f ( x ) = ( 1 / x ) - a .
ξ = 1 / a .
f ( x ) = g ( x ) - a ,
g ( x ) = g ( x 0 ) + g ( x 0 ) 1 ! ( x - x 0 ) + g ( x 0 ) 2 ! ( x - x 0 ) 2 + .
g ( x ) = x - 1 , g ( x ) = - x - 2 , g ( x ) = 2 x - 3 ,
g ( n ) ( x 0 ) n ! = ( - 1 ) n 2 n + 1
lim n [ g ( n ) ( 0.5 ) ( x - 0.5 ) n n ! ] / [ g ( n - 1 ) ( 0.5 ) ( x - 0.5 ) n - 1 ( n - 1 ) ! ] = lim n 2 ( x - 0.5 ) n = 0 ,
x 1 = x s - ( 1 / x s - a ) ( - 1 / x s 2 ) = ( 2 - a x s ) x s = 2 x 2 - a x s 2 , x 1 = 2 x 1 - a x 1 2 .

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