Abstract

As feature sizes decrease to the submicrometer regime and clock rates increase to the multigigahertz range, the limited bandwidth at higher bit rates and longer communication distances in electrical interconnects will create a major bandwidth imbalance in future high-performance computing (HPC) systems. We explore the application of an optoelectronic interconnect for the design of flexible, high-bandwidth, reconfigurable and adaptive interconnection architectures for chip-to-chip and board-to-board HPC systems. Reconfigurability is realized by interconnecting arrays of optical transmitters, and adaptivity is implemented by a dynamic bandwidth reallocation (DBR) technique that balances the load on each communication channel. We evaluate a DBR technique, the lockstep (LS) protocol, that monitors traffic intensities, reallocates bandwidth, and adapts to changes in communication patterns. We incorporate this DBR technique into a detailed discrete-event network simulator to evaluate the performance for uniform, nonuniform, and permutation communication patterns. Simulation results indicate that, without reconfiguration techniques being applied, optical based system architecture shows better performance than electrical interconnects for uniform and nonuniform patterns; with reconfiguration techniques being applied, the dynamically reconfigurable optoelectronic interconnect provides much better performance for all communication patterns. Based on the performance study, the reconfigured architecture shows 30%50% increased throughput and 50%75% reduced network latency compared with HPC electrical networks.

© 2009 Optical Society of America

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2008 (1)

A. Kodi and A. Louri, “Optisim: a system simulation methodology in optically interconnected HPC systems,” IEEE Micro 28, 22-36 (2008).
[CrossRef]

2006 (1)

2005 (2)

A. Shacham, B. Small, O. Liboiron-Ladouceur, and K. Bergman, “A fully implemented 12×12 data vortex optical packet switching interconnection network,” J. Lightwave Technol. 23, 3066-3075 (2005).
[CrossRef]

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kutcha, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev. 49, 755-775 (2005).
[CrossRef]

2004 (3)

2003 (2)

T. S. D. Huang, A. Landin, R. Lytel, and H. L. Davidson, “Optical interconnects: out of the box forever?,” IEEE J. Sel. Top. Quantum Electron. 9, 614-623 (2003).
[CrossRef]

F. Petrini, E. Frachtenberg, A. Hoisie, and S. Coll, “Performance evaluation of the quadrics interconnection network,” Cluster Comput. 6, 125-142 (2003).
[CrossRef]

2002 (1)

S. S. Mukherjee, P. Bannon, S. Lang, A. Spink, and D. Webb, “The Alpha 21364 network architecture,” IEEE Micro 22, 26-35 (2002).
[CrossRef]

2000 (3)

A. V. Krishnamoorthy, K. W. Goossen, L. M. F. Chirovsky, R. G. Rozier, P. Chandramani, S. P. Hui, J. Lopata, J. A. Walker, and L. A. D'Asaro, “16×16 VCSEL array flip-chip bonded to CMOS VLSI circuit,” IEEE Photon. Technol. Lett. 12, 1073-1075 (2000).
[CrossRef]

J. Collet, D. Litaize, J. V. Campenhut, C. Jesshope, M. Desmulliez, H. Thienpont, J. Goodman, and A. Louri, “Architectural approach to the role of optics in monoprocessor and multiprocessor machines,” Appl. Opt. 39, 671-682 (2000).
[CrossRef]

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE 88, 728-749 (2000).
[CrossRef]

1998 (1)

A. V. Krishnamoorthy and K. W. Goossen, “Optoelectronic-VLSI: photonics integrated with VLSI circuits,” IEEE J. Sel. Top. Quantum Electron. 4, 899-912 (1998).
[CrossRef]

1997 (1)

M. Galles, “Spider: a high-speed network interconnect,” IEEE Micro 17, 34-39 (1997).
[CrossRef]

1996 (1)

P. Dowd, J. Perreault, J. Chu, D. Hoffmeister, R. Minnich, D. Burns, F. Hady, Y.-J. Chen, M. Dagenais, and D. Stone, “LIGHTNING: network and systems architecture,” J. Lightwave Technol. 14, 1371-1387 (1996).
[CrossRef]

1994 (1)

C. M. Qiao, R. Melhem, D. Chiarulli, and S. Levitan, “Dynamic reconfiguration of optically interconnected networks with time-division multiplexing,” J. Parallel Distrib. Comput. 22, 268-278 (1994).
[CrossRef]

Albonesi, D.

N. Kirman, M. Kirman, R. Dokania, J. Martínez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proceedings of the 39th International Symposium on Microarchitecture (IEEE, 2006).

Alduino, A.

E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, “Optical interconnect system integration for ultra-short-reach applications,” Intel Technol. J. 8, 114-127(2004).

Ali, M. E.

Apsel, A.

N. Kirman, M. Kirman, R. Dokania, J. Martínez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proceedings of the 39th International Symposium on Microarchitecture (IEEE, 2006).

Baks, C.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Bannon, P.

S. S. Mukherjee, P. Bannon, S. Lang, A. Spink, and D. Webb, “The Alpha 21364 network architecture,” IEEE Micro 22, 26-35 (2002).
[CrossRef]

Barnett, B.

E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, “Optical interconnect system integration for ultra-short-reach applications,” Intel Technol. J. 8, 114-127(2004).

Benner, A. F.

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kutcha, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev. 49, 755-775 (2005).
[CrossRef]

Bergman, K.

Braunisch, H.

E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, “Optical interconnect system integration for ultra-short-reach applications,” Intel Technol. J. 8, 114-127(2004).

Burns, D.

P. Dowd, J. Perreault, J. Chu, D. Hoffmeister, R. Minnich, D. Burns, F. Hady, Y.-J. Chen, M. Dagenais, and D. Stone, “LIGHTNING: network and systems architecture,” J. Lightwave Technol. 14, 1371-1387 (1996).
[CrossRef]

Campenhut, J. V.

Chamberlain, R.

P. Krishnamurthy, R. Chamberlain, and M. Franklin, “Dynamic reconfiguration of an optical interconnect,” presented at 36th Annual Simulation Symposium (Society for Modeling and Simulation International, 2003).

Chandramani, P.

A. V. Krishnamoorthy, K. W. Goossen, L. M. F. Chirovsky, R. G. Rozier, P. Chandramani, S. P. Hui, J. Lopata, J. A. Walker, and L. A. D'Asaro, “16×16 VCSEL array flip-chip bonded to CMOS VLSI circuit,” IEEE Photon. Technol. Lett. 12, 1073-1075 (2000).
[CrossRef]

Chen, X.

X. Chen, L.-S. Peh, G.-Y. Wei, Y.-K. Huang, and P. Pruncal, “Exploring the design space of power-aware opto-electronic networked systems,” in Proceedings of the 11th International Symposium on High-Performance Computer Architecture (HPCA-11) (IEEE, 2005), pp. 120-131.

Chen, Y.-J.

P. Dowd, J. Perreault, J. Chu, D. Hoffmeister, R. Minnich, D. Burns, F. Hady, Y.-J. Chen, M. Dagenais, and D. Stone, “LIGHTNING: network and systems architecture,” J. Lightwave Technol. 14, 1371-1387 (1996).
[CrossRef]

Chiarulli, D.

C. M. Qiao, R. Melhem, D. Chiarulli, and S. Levitan, “Dynamic reconfiguration of optically interconnected networks with time-division multiplexing,” J. Parallel Distrib. Comput. 22, 268-278 (1994).
[CrossRef]

Chirovsky, L. M. F.

A. V. Krishnamoorthy, K. W. Goossen, L. M. F. Chirovsky, R. G. Rozier, P. Chandramani, S. P. Hui, J. Lopata, J. A. Walker, and L. A. D'Asaro, “16×16 VCSEL array flip-chip bonded to CMOS VLSI circuit,” IEEE Photon. Technol. Lett. 12, 1073-1075 (2000).
[CrossRef]

Chu, J.

P. Dowd, J. Perreault, J. Chu, D. Hoffmeister, R. Minnich, D. Burns, F. Hady, Y.-J. Chen, M. Dagenais, and D. Stone, “LIGHTNING: network and systems architecture,” J. Lightwave Technol. 14, 1371-1387 (1996).
[CrossRef]

Coll, S.

F. Petrini, E. Frachtenberg, A. Hoisie, and S. Coll, “Performance evaluation of the quadrics interconnection network,” Cluster Comput. 6, 125-142 (2003).
[CrossRef]

Collet, J.

Culler, D. E.

D. E. Culler, J. P. Singh, and A. Gupta, Parallel Computer Architecture: a Hardware/Software Approach (Morgan Kaufmann, 1999).

Dagenais, M.

P. Dowd, J. Perreault, J. Chu, D. Hoffmeister, R. Minnich, D. Burns, F. Hady, Y.-J. Chen, M. Dagenais, and D. Stone, “LIGHTNING: network and systems architecture,” J. Lightwave Technol. 14, 1371-1387 (1996).
[CrossRef]

Dally, W. J.

W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks (Morgan Kaufmann, 2004).

D'Asaro, L. A.

A. V. Krishnamoorthy, K. W. Goossen, L. M. F. Chirovsky, R. G. Rozier, P. Chandramani, S. P. Hui, J. Lopata, J. A. Walker, and L. A. D'Asaro, “16×16 VCSEL array flip-chip bonded to CMOS VLSI circuit,” IEEE Photon. Technol. Lett. 12, 1073-1075 (2000).
[CrossRef]

Davidson, H. L.

T. S. D. Huang, A. Landin, R. Lytel, and H. L. Davidson, “Optical interconnects: out of the box forever?,” IEEE J. Sel. Top. Quantum Electron. 9, 614-623 (2003).
[CrossRef]

Desmulliez, M.

Dokania, R.

N. Kirman, M. Kirman, R. Dokania, J. Martínez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proceedings of the 39th International Symposium on Microarchitecture (IEEE, 2006).

Dolfi, D. W.

Dowd, P.

P. Dowd, J. Perreault, J. Chu, D. Hoffmeister, R. Minnich, D. Burns, F. Hady, Y.-J. Chen, M. Dagenais, and D. Stone, “LIGHTNING: network and systems architecture,” J. Lightwave Technol. 14, 1371-1387 (1996).
[CrossRef]

Flower, G. M.

Frachtenberg, E.

F. Petrini, E. Frachtenberg, A. Hoisie, and S. Coll, “Performance evaluation of the quadrics interconnection network,” Cluster Comput. 6, 125-142 (2003).
[CrossRef]

Franklin, M.

P. Krishnamurthy, R. Chamberlain, and M. Franklin, “Dynamic reconfiguration of an optical interconnect,” presented at 36th Annual Simulation Symposium (Society for Modeling and Simulation International, 2003).

Galles, M.

M. Galles, “Spider: a high-speed network interconnect,” IEEE Micro 17, 34-39 (1997).
[CrossRef]

Goodman, J.

Goossen, K. W.

A. V. Krishnamoorthy, K. W. Goossen, L. M. F. Chirovsky, R. G. Rozier, P. Chandramani, S. P. Hui, J. Lopata, J. A. Walker, and L. A. D'Asaro, “16×16 VCSEL array flip-chip bonded to CMOS VLSI circuit,” IEEE Photon. Technol. Lett. 12, 1073-1075 (2000).
[CrossRef]

A. V. Krishnamoorthy and K. W. Goossen, “Optoelectronic-VLSI: photonics integrated with VLSI circuits,” IEEE J. Sel. Top. Quantum Electron. 4, 899-912 (1998).
[CrossRef]

Gowda, S.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Graham, L.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Gupta, A.

D. E. Culler, J. P. Singh, and A. Gupta, Parallel Computer Architecture: a Hardware/Software Approach (Morgan Kaufmann, 1999).

Hady, F.

P. Dowd, J. Perreault, J. Chu, D. Hoffmeister, R. Minnich, D. Burns, F. Hady, Y.-J. Chen, M. Dagenais, and D. Stone, “LIGHTNING: network and systems architecture,” J. Lightwave Technol. 14, 1371-1387 (1996).
[CrossRef]

Hajimiri, A.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Haymes, C.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Heck, J.

E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, “Optical interconnect system integration for ultra-short-reach applications,” Intel Technol. J. 8, 114-127(2004).

Hoffmeister, D.

P. Dowd, J. Perreault, J. Chu, D. Hoffmeister, R. Minnich, D. Burns, F. Hady, Y.-J. Chen, M. Dagenais, and D. Stone, “LIGHTNING: network and systems architecture,” J. Lightwave Technol. 14, 1371-1387 (1996).
[CrossRef]

Hoisie, A.

F. Petrini, E. Frachtenberg, A. Hoisie, and S. Coll, “Performance evaluation of the quadrics interconnection network,” Cluster Comput. 6, 125-142 (2003).
[CrossRef]

Huang, T. S. D.

T. S. D. Huang, A. Landin, R. Lytel, and H. L. Davidson, “Optical interconnects: out of the box forever?,” IEEE J. Sel. Top. Quantum Electron. 9, 614-623 (2003).
[CrossRef]

Huang, Y.-K.

X. Chen, L.-S. Peh, G.-Y. Wei, Y.-K. Huang, and P. Pruncal, “Exploring the design space of power-aware opto-electronic networked systems,” in Proceedings of the 11th International Symposium on High-Performance Computer Architecture (HPCA-11) (IEEE, 2005), pp. 120-131.

Hui, S. P.

A. V. Krishnamoorthy, K. W. Goossen, L. M. F. Chirovsky, R. G. Rozier, P. Chandramani, S. P. Hui, J. Lopata, J. A. Walker, and L. A. D'Asaro, “16×16 VCSEL array flip-chip bonded to CMOS VLSI circuit,” IEEE Photon. Technol. Lett. 12, 1073-1075 (2000).
[CrossRef]

Ignatowski, M.

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kutcha, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev. 49, 755-775 (2005).
[CrossRef]

Jesshope, C.

Jewell, J.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Jump, J. R.

J. R. Jump, “Yacsim reference manual,” Rice University; available at http://www-ece.rice.edu/ rppt.html (1993).

Kash, J.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Kash, J. A.

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kutcha, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev. 49, 755-775 (2005).
[CrossRef]

Kirman, M.

N. Kirman, M. Kirman, R. Dokania, J. Martínez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proceedings of the 39th International Symposium on Microarchitecture (IEEE, 2006).

Kirman, N.

N. Kirman, M. Kirman, R. Dokania, J. Martínez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proceedings of the 39th International Symposium on Microarchitecture (IEEE, 2006).

Kodi, A.

A. Kodi and A. Louri, “Optisim: a system simulation methodology in optically interconnected HPC systems,” IEEE Micro 28, 22-36 (2008).
[CrossRef]

Kodi, A. K.

A. K. Kodi and A. Louri, “RAPID for high-performance computing systems: architecture and performance evaluation,” Appl. Opt. 45, 6326-6334 (2006).
[CrossRef] [PubMed]

A. K. Kodi and A. Louri, “RAPID: reconfigurable and scalable all-photonic interconnect for distributed shared memory multiprocessors,” J. Lightwave Technol. 22, 2101-2110 (2004).
[CrossRef]

A. K. Kodi and A. Louri, “A new technique for dynamic bandwidth re-allocation in optically high-performance computing systems,” in Proceedings of the 14th Annual IEEE Symposium on Hot Interconnects (IEEE, 2006), pp. 31-36..

A. K. Kodi and A. Louri, “Power aware bandwidth reconfigurable optical interconnects for HPC systems,” in Proceedings of the 21st IEEE International Parallel and Distributed Symposium (IPDPS'07) (IEEE, 2007), p. 81.
[CrossRef]

Krishnamoorthy, A. V.

A. V. Krishnamoorthy, K. W. Goossen, L. M. F. Chirovsky, R. G. Rozier, P. Chandramani, S. P. Hui, J. Lopata, J. A. Walker, and L. A. D'Asaro, “16×16 VCSEL array flip-chip bonded to CMOS VLSI circuit,” IEEE Photon. Technol. Lett. 12, 1073-1075 (2000).
[CrossRef]

A. V. Krishnamoorthy and K. W. Goossen, “Optoelectronic-VLSI: photonics integrated with VLSI circuits,” IEEE J. Sel. Top. Quantum Electron. 4, 899-912 (1998).
[CrossRef]

Krishnamurthy, P.

P. Krishnamurthy, R. Chamberlain, and M. Franklin, “Dynamic reconfiguration of an optical interconnect,” presented at 36th Annual Simulation Symposium (Society for Modeling and Simulation International, 2003).

Kucharski, D.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Kuchta, D.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Kutcha, D. M.

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kutcha, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev. 49, 755-775 (2005).
[CrossRef]

Kwark, Y.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Landin, A.

T. S. D. Huang, A. Landin, R. Lytel, and H. L. Davidson, “Optical interconnects: out of the box forever?,” IEEE J. Sel. Top. Quantum Electron. 9, 614-623 (2003).
[CrossRef]

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S. S. Mukherjee, P. Bannon, S. Lang, A. Spink, and D. Webb, “The Alpha 21364 network architecture,” IEEE Micro 22, 26-35 (2002).
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Lenoski, D. E.

D. E. Lenoski and W.-D. Weber, Scalable Shared-Memory Multiprocessing (Morgan Kaufmann, 1995).

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Levitan, S.

C. M. Qiao, R. Melhem, D. Chiarulli, and S. Levitan, “Dynamic reconfiguration of optically interconnected networks with time-division multiplexing,” J. Parallel Distrib. Comput. 22, 268-278 (1994).
[CrossRef]

Liboiron-Ladouceur, O.

Litaize, D.

Liu, A.

E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, “Optical interconnect system integration for ultra-short-reach applications,” Intel Technol. J. 8, 114-127(2004).

Lopata, J.

A. V. Krishnamoorthy, K. W. Goossen, L. M. F. Chirovsky, R. G. Rozier, P. Chandramani, S. P. Hui, J. Lopata, J. A. Walker, and L. A. D'Asaro, “16×16 VCSEL array flip-chip bonded to CMOS VLSI circuit,” IEEE Photon. Technol. Lett. 12, 1073-1075 (2000).
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Louri, A.

A. Kodi and A. Louri, “Optisim: a system simulation methodology in optically interconnected HPC systems,” IEEE Micro 28, 22-36 (2008).
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A. K. Kodi and A. Louri, “RAPID for high-performance computing systems: architecture and performance evaluation,” Appl. Opt. 45, 6326-6334 (2006).
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A. K. Kodi and A. Louri, “RAPID: reconfigurable and scalable all-photonic interconnect for distributed shared memory multiprocessors,” J. Lightwave Technol. 22, 2101-2110 (2004).
[CrossRef]

J. Collet, D. Litaize, J. V. Campenhut, C. Jesshope, M. Desmulliez, H. Thienpont, J. Goodman, and A. Louri, “Architectural approach to the role of optics in monoprocessor and multiprocessor machines,” Appl. Opt. 39, 671-682 (2000).
[CrossRef]

A. K. Kodi and A. Louri, “A new technique for dynamic bandwidth re-allocation in optically high-performance computing systems,” in Proceedings of the 14th Annual IEEE Symposium on Hot Interconnects (IEEE, 2006), pp. 31-36..

A. K. Kodi and A. Louri, “Power aware bandwidth reconfigurable optical interconnects for HPC systems,” in Proceedings of the 21st IEEE International Parallel and Distributed Symposium (IPDPS'07) (IEEE, 2007), p. 81.
[CrossRef]

Lu, D.

E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, “Optical interconnect system integration for ultra-short-reach applications,” Intel Technol. J. 8, 114-127(2004).

Lytel, R.

T. S. D. Huang, A. Landin, R. Lytel, and H. L. Davidson, “Optical interconnects: out of the box forever?,” IEEE J. Sel. Top. Quantum Electron. 9, 614-623 (2003).
[CrossRef]

Madhavan, B.

Martínez, J.

N. Kirman, M. Kirman, R. Dokania, J. Martínez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proceedings of the 39th International Symposium on Microarchitecture (IEEE, 2006).

Melhem, R.

C. M. Qiao, R. Melhem, D. Chiarulli, and S. Levitan, “Dynamic reconfiguration of optically interconnected networks with time-division multiplexing,” J. Parallel Distrib. Comput. 22, 268-278 (1994).
[CrossRef]

Miller, D. A. B.

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE 88, 728-749 (2000).
[CrossRef]

Minnich, R.

P. Dowd, J. Perreault, J. Chu, D. Hoffmeister, R. Minnich, D. Burns, F. Hady, Y.-J. Chen, M. Dagenais, and D. Stone, “LIGHTNING: network and systems architecture,” J. Lightwave Technol. 14, 1371-1387 (1996).
[CrossRef]

Mohammed, E.

E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, “Optical interconnect system integration for ultra-short-reach applications,” Intel Technol. J. 8, 114-127(2004).

Mooney, R.

E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, “Optical interconnect system integration for ultra-short-reach applications,” Intel Technol. J. 8, 114-127(2004).

Mukherjee, S. S.

S. S. Mukherjee, P. Bannon, S. Lang, A. Spink, and D. Webb, “The Alpha 21364 network architecture,” IEEE Micro 22, 26-35 (2002).
[CrossRef]

Panotopoulos, G.

Peh, L.-S.

X. Chen, L.-S. Peh, G.-Y. Wei, Y.-K. Huang, and P. Pruncal, “Exploring the design space of power-aware opto-electronic networked systems,” in Proceedings of the 11th International Symposium on High-Performance Computer Architecture (HPCA-11) (IEEE, 2005), pp. 120-131.

Pepeljugoski, P.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Perreault, J.

P. Dowd, J. Perreault, J. Chu, D. Hoffmeister, R. Minnich, D. Burns, F. Hady, Y.-J. Chen, M. Dagenais, and D. Stone, “LIGHTNING: network and systems architecture,” J. Lightwave Technol. 14, 1371-1387 (1996).
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Petrini, F.

F. Petrini, E. Frachtenberg, A. Hoisie, and S. Coll, “Performance evaluation of the quadrics interconnection network,” Cluster Comput. 6, 125-142 (2003).
[CrossRef]

Pruncal, P.

X. Chen, L.-S. Peh, G.-Y. Wei, Y.-K. Huang, and P. Pruncal, “Exploring the design space of power-aware opto-electronic networked systems,” in Proceedings of the 11th International Symposium on High-Performance Computer Architecture (HPCA-11) (IEEE, 2005), pp. 120-131.

Qiao, C. M.

C. M. Qiao, R. Melhem, D. Chiarulli, and S. Levitan, “Dynamic reconfiguration of optically interconnected networks with time-division multiplexing,” J. Parallel Distrib. Comput. 22, 268-278 (1994).
[CrossRef]

Ritter, M. B.

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kutcha, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev. 49, 755-775 (2005).
[CrossRef]

Rozier, R. G.

A. V. Krishnamoorthy, K. W. Goossen, L. M. F. Chirovsky, R. G. Rozier, P. Chandramani, S. P. Hui, J. Lopata, J. A. Walker, and L. A. D'Asaro, “16×16 VCSEL array flip-chip bonded to CMOS VLSI circuit,” IEEE Photon. Technol. Lett. 12, 1073-1075 (2000).
[CrossRef]

Schaub, J.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Schuster, C.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Shacham, A.

Singh, J. P.

D. E. Culler, J. P. Singh, and A. Gupta, Parallel Computer Architecture: a Hardware/Software Approach (Morgan Kaufmann, 1999).

Small, B.

Spink, A.

S. S. Mukherjee, P. Bannon, S. Lang, A. Spink, and D. Webb, “The Alpha 21364 network architecture,” IEEE Micro 22, 26-35 (2002).
[CrossRef]

Stone, D.

P. Dowd, J. Perreault, J. Chu, D. Hoffmeister, R. Minnich, D. Burns, F. Hady, Y.-J. Chen, M. Dagenais, and D. Stone, “LIGHTNING: network and systems architecture,” J. Lightwave Technol. 14, 1371-1387 (1996).
[CrossRef]

Thienpont, H.

Thomas, T.

E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, “Optical interconnect system integration for ultra-short-reach applications,” Intel Technol. J. 8, 114-127(2004).

Tierno, J.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Towles, B.

W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks (Morgan Kaufmann, 2004).

Vandentop, G.

E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, “Optical interconnect system integration for ultra-short-reach applications,” Intel Technol. J. 8, 114-127(2004).

Walker, J. A.

A. V. Krishnamoorthy, K. W. Goossen, L. M. F. Chirovsky, R. G. Rozier, P. Chandramani, S. P. Hui, J. Lopata, J. A. Walker, and L. A. D'Asaro, “16×16 VCSEL array flip-chip bonded to CMOS VLSI circuit,” IEEE Photon. Technol. Lett. 12, 1073-1075 (2000).
[CrossRef]

Watkins, M.

N. Kirman, M. Kirman, R. Dokania, J. Martínez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proceedings of the 39th International Symposium on Microarchitecture (IEEE, 2006).

Webb, D.

S. S. Mukherjee, P. Bannon, S. Lang, A. Spink, and D. Webb, “The Alpha 21364 network architecture,” IEEE Micro 22, 26-35 (2002).
[CrossRef]

Weber, W.-D.

D. E. Lenoski and W.-D. Weber, Scalable Shared-Memory Multiprocessing (Morgan Kaufmann, 1995).

Wei, G.-Y.

X. Chen, L.-S. Peh, G.-Y. Wei, Y.-K. Huang, and P. Pruncal, “Exploring the design space of power-aware opto-electronic networked systems,” in Proceedings of the 11th International Symposium on High-Performance Computer Architecture (HPCA-11) (IEEE, 2005), pp. 120-131.

Wu, H.

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Young, I.

E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, “Optical interconnect system integration for ultra-short-reach applications,” Intel Technol. J. 8, 114-127(2004).

Appl. Opt. (2)

Cluster Comput. (1)

F. Petrini, E. Frachtenberg, A. Hoisie, and S. Coll, “Performance evaluation of the quadrics interconnection network,” Cluster Comput. 6, 125-142 (2003).
[CrossRef]

IBM J. Res. Dev. (1)

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kutcha, and M. B. Ritter, “Exploitation of optical interconnects in future server architectures,” IBM J. Res. Dev. 49, 755-775 (2005).
[CrossRef]

IEEE J. Sel. Top. Quantum Electron. (2)

T. S. D. Huang, A. Landin, R. Lytel, and H. L. Davidson, “Optical interconnects: out of the box forever?,” IEEE J. Sel. Top. Quantum Electron. 9, 614-623 (2003).
[CrossRef]

A. V. Krishnamoorthy and K. W. Goossen, “Optoelectronic-VLSI: photonics integrated with VLSI circuits,” IEEE J. Sel. Top. Quantum Electron. 4, 899-912 (1998).
[CrossRef]

IEEE Micro (3)

A. Kodi and A. Louri, “Optisim: a system simulation methodology in optically interconnected HPC systems,” IEEE Micro 28, 22-36 (2008).
[CrossRef]

S. S. Mukherjee, P. Bannon, S. Lang, A. Spink, and D. Webb, “The Alpha 21364 network architecture,” IEEE Micro 22, 26-35 (2002).
[CrossRef]

M. Galles, “Spider: a high-speed network interconnect,” IEEE Micro 17, 34-39 (1997).
[CrossRef]

IEEE Photon. Technol. Lett. (1)

A. V. Krishnamoorthy, K. W. Goossen, L. M. F. Chirovsky, R. G. Rozier, P. Chandramani, S. P. Hui, J. Lopata, J. A. Walker, and L. A. D'Asaro, “16×16 VCSEL array flip-chip bonded to CMOS VLSI circuit,” IEEE Photon. Technol. Lett. 12, 1073-1075 (2000).
[CrossRef]

Intel Technol. J. (1)

E. Mohammed, A. Alduino, T. Thomas, H. Braunisch, D. Lu, J. Heck, A. Liu, I. Young, B. Barnett, G. Vandentop, and R. Mooney, “Optical interconnect system integration for ultra-short-reach applications,” Intel Technol. J. 8, 114-127(2004).

J. Lightwave Technol. (4)

J. Parallel Distrib. Comput. (1)

C. M. Qiao, R. Melhem, D. Chiarulli, and S. Levitan, “Dynamic reconfiguration of optically interconnected networks with time-division multiplexing,” J. Parallel Distrib. Comput. 22, 268-278 (1994).
[CrossRef]

Proc. IEEE (1)

D. A. B. Miller, “Rationale and challenges for optical interconnects to electronic chips,” Proc. IEEE 88, 728-749 (2000).
[CrossRef]

Other (12)

A. K. Kodi and A. Louri, “A new technique for dynamic bandwidth re-allocation in optically high-performance computing systems,” in Proceedings of the 14th Annual IEEE Symposium on Hot Interconnects (IEEE, 2006), pp. 31-36..

A. K. Kodi and A. Louri, “Power aware bandwidth reconfigurable optical interconnects for HPC systems,” in Proceedings of the 21st IEEE International Parallel and Distributed Symposium (IPDPS'07) (IEEE, 2007), p. 81.
[CrossRef]

W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks (Morgan Kaufmann, 2004).

N. Kirman, M. Kirman, R. Dokania, J. Martínez, A. Apsel, M. Watkins, and D. Albonesi, “Leveraging optical technology in future bus-based chip multiprocessors,” in Proceedings of the 39th International Symposium on Microarchitecture (IEEE, 2006).

“Closing the gap between peak and achievable performance in high performance computing,” Tech. Rep. WP-0020404, CRAY Incorporated, Seattle, Washington (2004).

D. E. Lenoski and W.-D. Weber, Scalable Shared-Memory Multiprocessing (Morgan Kaufmann, 1995).

P. Krishnamurthy, R. Chamberlain, and M. Franklin, “Dynamic reconfiguration of an optical interconnect,” presented at 36th Annual Simulation Symposium (Society for Modeling and Simulation International, 2003).

D. E. Culler, J. P. Singh, and A. Gupta, Parallel Computer Architecture: a Hardware/Software Approach (Morgan Kaufmann, 1999).

J. Kash, C. Baks, S. Gowda, L. Graham, A. Hajimiri, C. Haymes, J. Jewell, D. Kucharski, D. Kuchta, Y. Kwark, P. Pepeljugoski, J. Schaub, C. Schuster, J. Tierno, and H. Wu, “Bringing optics inside the box: recent progress and future trends,” presented at the 16th Annual Meeting of the IEEE/LEOS (2003), p. 23.

Mellanox Technologies, http://www.mellanox.com/.

X. Chen, L.-S. Peh, G.-Y. Wei, Y.-K. Huang, and P. Pruncal, “Exploring the design space of power-aware opto-electronic networked systems,” in Proceedings of the 11th International Symposium on High-Performance Computer Architecture (HPCA-11) (IEEE, 2005), pp. 120-131.

J. R. Jump, “Yacsim reference manual,” Rice University; available at http://www-ece.rice.edu/ rppt.html (1993).

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Figures (9)

Fig. 1
Fig. 1

(a) Schematic of the E-RAPID architecture and (b) conceptual diagram of the E-RAPID network.

Fig. 2
Fig. 2

Onboard interconnect in E-RAPID; board 0 is shown as an example, which consists of network send and receive pairs along with optical transmitters and receivers.

Fig. 3
Fig. 3

Static RWA in E-RAPID for interboard communication. The example shows four boards, each consisting of four nodes connected within a cluster.

Fig. 4
Fig. 4

Proposed E-RAPID architecture with a reconfiguration controller and a LC.

Fig. 5
Fig. 5

(a) Nonreconfigured communication in E-RAPID, (b) reconfigured communication in E-RAPID based on the same optical transmitter queue, (c) a reconfigured communication in E-RAPID based on different optical transmitter queues.

Fig. 6
Fig. 6

Proposed technology for reconfiguration using passive couplers and an array of transmitters.

Fig. 7
Fig. 7

Reconfiguration algorithm implementation: (a) the LR (link request/response) packet sent to all the nodes within a board and (b) the BR (board request/response) packet sent to all the boards within a cluster.

Fig. 8
Fig. 8

Throughput for 64 nodes with reconfiguration for Uniform, Bit-Reversal, Butterfly, Complement, Matrix Transpose, and Perfect Shuffle traffic patterns. The networks compared are Torus, Fatree, Hypercube, and RAPID variations: RAPID, M-RAPID, E-RAPID, and E-RAPID (recon).

Fig. 9
Fig. 9

Latency for 64 nodes with reconfiguration for Uniform, Bit-Reversal, Butterfly, Complement, Matrix Transpose, and Perfect Shuffle traffic patterns. The networks compared are Torus, Fatree, Hypercube, and RAPID variations: RAPID, M-RAPID, E-RAPID, and E-RAPID (recon).

Tables (1)

Tables Icon

Table 1 LS Algorithm for DBR Implementation

Metrics