Free-space photonic switching architectures based on extended generalized shuffle networks

Thomas J. Cloonan; Gaylord W. Richards; Anthony L. Lentine; Frederick B. McCormick; John R. Erickson

doi:10.1364/AO.31.007471

Applied Optics
Vol. 31,
Issue 35,
pp. 7471-7492
(1992)
•https://doi.org/10.1364/AO.31.007471

Free-space photonic switching architectures based on extended generalized shuffle networks

Thomas J. Cloonan, Gaylord W. Richards, Anthony L. Lentine, Frederick B. McCormick, and John R. Erickson

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Thomas J. Cloonan, Gaylord W. Richards, Anthony L. Lentine, Frederick B. McCormick, and John R. Erickson, "Free-space photonic switching architectures based on extended generalized shuffle networks," Appl. Opt. 31, 7471-7492 (1992)

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Abstract

A new class of networks that is well suited for free-space photonic switching applications is described. These networks are known as extended generalized shuffle networks. It is shown that these networks can provide low blocking probabilities while requiring low hardware costs. In fact, if sufficient hardware is added to these networks, they become strictly nonblocking networks (with blocking probabilities equal to zero). The hardware cost of an extended generalized shuffle network can be modified to yield any desired blocking probability, so cost-effective designs are possible. In addition, it is shown that these networks are extremely fault tolerant, and they can also be designed to have high system availabilities. Because the networks can use various types of interconnections to connect the nodes and because the nodes can have various types of functionality, these networks also provide high degrees of flexibility that can be used to optimize a free-space photonic design. The design of extended generalized shuffle networks based on a particular node type that is easy to implement with symmetric self-electro-optic-effect devices is studied.

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Number of Switching Section Stages S	Minimum Required Fan-out [Based on Inequality (4)] F	Minimum Required Fan-out (3-D Implementation) F′	Number of Required S-SEED Arrays A′	Required Dimensions of S-SEED Arrays D′
0	256	512	19	256 × 512
1	256	512	21	256 × 512
2	192	512	23	256 × 512
3	160	512	25	256 × 512
4	112	128	23	128 × 256
5	88	128	25	128 × 256
6	60	128	27	128 × 256
7	46	128	29	128 × 256
8	31	32	27	64 × 128
9	25	32	29	64 × 128
10	19	32	31	64 × 128
11	17	32	33	64 × 128
12	14	32	35	64 × 128
13	14	32	37	64 × 128
14	14	32	39	64 × 128

Number of Network Inputs N	Number of Logic Gates per Device Array	Number of Device Arrays

		Nonblocking	P(B) < 10⁻⁸
16	8 × 16	13	13
32	16 × 32	17	15
	8 × 16		27
64	32 × 64	19	17
	16 × 32		21
128	32 × 64	27	21
256	64 × 128	27	23
	32 × 64		27
512	64 × 128	37	27
1024	128 × 256	37	29
	64 × 128		31
2048	256 × 512	39	29
	128 × 256		33
4096	256 × 512	45	33

Network Design from Section 7	Number of Pipes Q	Number of S-SEED Arrays per Pipe A′	Total Number of S-SEED Arrays QA′	Required Dimensions of S-SEED Arrays D′	Blocking Probability with all Pipes Active P(B)	Blocking Probability with One Pipe Disabled P(B)
Network Design A (F_tot = 16, S = 10)	2 (F_elect = 2)	27	54	32 × 64 (F_pipe = 8)	< 10⁻⁸	< 10⁻⁸
Network Design B (F_tot = 16, S = 8)	2 (F_elect = 2)	23	46	32 × 64 (F_pipe = 8)	< 10⁻⁸	4.4 × 10⁻³
Network Design C (F_tot = 24, S = 7)	3 (F_elect = 3)	21	63	32 × 64 (F_pipe = 8)	< 10⁻⁸	3.0 × 10⁻⁷
Network Design D (F_tot = 32, S = 6)	4 (F_elect = 4)	19	76	3264 (F_pipe = 8)	< 10⁻⁸	3.0 × 10⁻⁷
Network Design E (F_tot = 6, S = 12)	3 (F_elect = 3)	27	81	16 × 32 (F_pipe = 2)	< 10⁻⁸	1.1 × 10⁻¹
Network Design F (F_tot = 8, S = 10)	4 (F_elect = 4)	23	92	16 × 32 (F_pipe = 2)	< 10⁻⁸	6.0 × 10⁻⁴

Network Design from Section 7	Number of Pipes Q	Number of S-SEED Arrays per Pipe A′	Total Number of S-SEED Arrays QA′	Required Dimensions of S-SEED Arrays D′	Minimum MTBF of Failable Components (yr)
Network Design A (F_tot = 16, S = 10)	2 (F_elect = 2)	27	54	32 × 64 (F_pipe = 8)	114.2
Network design B (F_tot = 16, S = 8)	2 (F_elect = 2)	23	46	32 × 64 (F_pipe = 8)	97.2
Network Design C (F_tot = 24, S = 7)	3 (F_elect = 3)	21	63	32 × 64 (F_pipe = 8)	8.0
Network Design D (F_tot = 32, S = 6)	4 (F_elect = 4)	19	76	32 × 64 (F_pipe = 8)	2.2
Network Design E (F_tot = 6, S = 12)	3 (F_elect = 3)	27	81	16 × 32 (F_pipe = 2)	10.4
Network Design F (F_tot = 8, S = 10)	4 (F_elect = 4)	23	92	16 × 32 (F_pipe = 2)	2.6

Number of Switching Section Stages S	Minimum Required Fan-out [Based on Inequality (4)] F	Minimum Required Fan-out (3-D Implementation) F′	Number of Required S-SEED Arrays A′	Required Dimensions of S-SEED Arrays D′
0	256	512	19	256 × 512
1	256	512	21	256 × 512
2	192	512	23	256 × 512
3	160	512	25	256 × 512
4	112	128	23	128 × 256
5	88	128	25	128 × 256
6	60	128	27	128 × 256
7	46	128	29	128 × 256
8	31	32	27	64 × 128
9	25	32	29	64 × 128
10	19	32	31	64 × 128
11	17	32	33	64 × 128
12	14	32	35	64 × 128
13	14	32	37	64 × 128
14	14	32	39	64 × 128

Abstract

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Tables (4)

Equations (29)

Applied Optics