Abstract

A 100G coherent receiver needs 4 56Gs/s ADCs and a tera-OPs DSP which dissipate only tens of watts. This paper discusses the forces pushing towards a single-chip CMOS solution, and the challenges in realising this.

© 2010 Optical Society of America

PDF Article
More Like This
56Gs/s ADC : Enabling 100GbE

Ian Dedic
OThT6 Optical Fiber Communication Conference (OFC) 2010

Challenges in implementing high-speed, low-power ADCs in CMOS

Lukas Kull
Th1B.2 Optical Fiber Communication Conference (OFC) 2015

Volterra Nonlinear Compensation of 100G Coherent OFDM with Baud-rate ADC, Tolerable Complexity and Low Intra-channel FWM/XPM Error Propagation

Rakefet Weidenfeld, Moshe Nazarathy, Reinhold Noe, and Isaac Shpantzer
OTuE3 Optical Fiber Communication Conference (OFC) 2010

References

You do not have subscription access to this journal. Citation lists with outbound citation links are available to subscribers only. You may subscribe either as an OSA member, or as an authorized user of your institution.

Contact your librarian or system administrator
or
Login to access OSA Member Subscription