Abstract

As chip multiprocessors (CMPs) scale to increasing numbers of cores and greater on-chip computational power, the gap between the available off-chip bandwidth and that which is required to appropriately feed the processors continues to widen under current memory access architectures. For many high-performance computing applications, the bandwidth available for both on- and offchip communications can play a vital role in efficient execution due to the use of data-parallel or data-centric algorithms. Electronic interconnected systems are increasingly bound by their communications infrastructure and the associated power dissipation of high-bandwidth data movement.

© 2010 Optical Society of America