With the increase of traffic in coherent optical communication systems, the proportion of resources (chip area) required by FEC in DSP chips is higher and higher. At the same time, pre-FEC performance is an explicit indicator of commercial competition. It is gradually improved in the evolution of the system, and the Shannon limit is approached step by step. The balanced design of FEC performance, area, and power consumption becomes a key point of the DSP chip of coherent optical communication.

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