Expand this Topic clickable element to expand a topic
Skip to content
Optica Publishing Group

FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON

Not Accessible

Your library or personal account may give you access

Abstract

A fixed-point deep neural network-based equalizer is implemented in FPGA and is shown to outperform MLSE in receiver sensitivity for 50 Gb/s PON downstream link. Embedded parallelization is proposed and verified to reduce hardware resources.

© 2020 The Author(s)

PDF Article
More Like This
Neural Network-based equalization in high-speed PONs

Lilin Yi, Tao Liao, Lei Xue, and Weisheng Hu
T4D.3 Optical Fiber Communication Conference (OFC) 2020

FPGA Implementation of Time-Interleaved Pruning Neural Network Equalizer for Short Reach Optical Interconnects

Mingyuan Li, Wenjia Zhang, and Zuyuan He
M4E.4 Asia Communications and Photonics Conference (ACP) 2021

Towards FPGA Implementation of Neural Network-Based Nonlinearity Mitigation Equalizers in Coherent Optical Transmission Systems

Pedro J. Freire, Michael Anderson, Bernhard Spinnler, Thomas Bex, Jaroslaw E. Prilepsky, Tobias A. Eriksson, Nelson Costa, Wolfgang Schairer, Michaela Blott, Antonio Napoli, and Sergei K. Turitsyn
We1C.2 European Conference and Exhibition on Optical Communication (ECOC) 2022

Select as filters


Select Topics Cancel
© Copyright 2024 | Optica Publishing Group. All Rights Reserved