Expand this Topic clickable element to expand a topic
Skip to content
Optica Publishing Group

56Gb/s PAM-4 VCSEL Transmitter With Quarter-Rate Forwarded Clock Using 65nm CMOS Circuits

Not Accessible

Your library or personal account may give you access

Abstract

A 56Gb/s PAM-4 VCSEL transmitter is demonstrated in 65nm CMOS. This paper also discusses different kinds of clocking architecture.

© 2019 The Author(s)

PDF Article
More Like This
A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die

Shang Hu, Tingyu Yao, Bozhi Yin, Chunyu Song, Lei Zhao, Juncheng Wang, Lei Wang, Rui Bai, Xin Wang, Tao Xia, Yi Peng, Binbin Yao, Yuan Li, Xuefeng Chen, Quan Pan, Nan Qi, and Patrick Yin Chiang
Tu3A.2 Optical Fiber Communication Conference (OFC) 2019

A 112 Gb/s PAM4 Transmitter with Silicon Photonics Microring Modulator and CMOS Driver

Hao Li, Ganesh Balamurugan, Meer Sakib, Jie Sun, Jeffery Driscoll, Ranjeet Kumar, Hasitha Jayatilleka, Haisheng Rong, James Jaussi, and Bryan Casper
Th4A.4 Optical Fiber Communication Conference (OFC) 2019

A 26-Gb/s 1.80-pJ/b CMOS-Driven Transmitter for 850-nm Common-Cathode VCSELs

M. Shibata and A. Chan Carusone
Tu3G.1 Optical Fiber Communication Conference (OFC) 2015

Select as filters


Select Topics Cancel
© Copyright 2024 | Optica Publishing Group. All Rights Reserved