Challenges in implementing high-speed, low-power ADCs in CMOS

Lukas Kull

doi:10.1364/OFC.2015.Th1B.2

Optical Fiber Communication Conference
OSA Technical Digest (online) (Optica Publishing Group, 2015),
paper Th1B.2
•https://doi.org/10.1364/OFC.2015.Th1B.2

Challenges in implementing high-speed, low-power ADCs in CMOS

Lukas Kull

Optical Fiber Communication Conference 2015

Los Angeles, California United States
22–26 March 2015
ISBN: 978-1-55752-937-4

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Practical ASIC Implementation (Th1B)

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L. Kull, "Challenges in implementing high-speed, low-power ADCs in CMOS," in Optical Fiber Communication Conference, OSA Technical Digest (online) (Optica Publishing Group, 2015), paper Th1B.2.

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Abstract

Challenges of CMOS ADC implementations for 100 Gb/s optical communication systems and beyond are highlighted. Limitations and opportunities of architectures and circuits are discussed based on a 56–90 GS/s 8 bit ADC in 32 nm SOI CMOS.

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