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Architectural Design Exploration of Chip-Scale Photonic Interconnection Networks Using Physical-Layer Analysis

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Abstract

We conduct an architectural exploration of three chip-scale photonic interconnection networks in a novel simulation environment, exploring insertion loss, crosstalk, and energy. The impact of these metrics is evaluated in the context of network performance.

© 2010 IEEE Communications Society, IEEE Photonics Society, OSA, Telcordia

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