Abstract
Optical array logic is studied as a methodological tool to design an electronic system for large scale information processing. This paper shows a design procedure to integrate parallel processing circuits on a silicon chip. We implement a specialized hardware to identify a gene network utilizing the proposed methodology.
© 2003 Optical Society of America
PDF ArticleMore Like This
Jun Tanida, Yasunori Nishimura, and Yoshiki Ichioka
PdP1 Optical Computing (IP) 1991
Jun Tanida, Yasuhiro Awatsuji, Nobuyuki Sakamoto, and Yoshiki Ichioka
OTuA.4 Optics in Computing (IP) 1997
Jun Tanida, Masaki Fukui, and Yoshiki Ichioka
WA3 Optical Computing (IP) 1989