The drive to design network equipment with multi-service capable interfaces has dramatically increased the complexity of the timing subsystems. In addition to standard SONET/SDH rates, these new systems must now support a diverse set of line rates including 10G Ethernet, 10G fibre channel, as well as the associated forward error correction (FEC) rates. Support for these new data rates is forcing timing subsystem designers to develop timing sources capable of providing an expanded set of low jitter, high frequency (>=622MHz) reference clocks for use across the data processing chain from physical layer to backplane transceiver.Using traditional approaches, this frequency diversity is supported by implementing multiple different phase lock loop (PLL) circuits built around high frequency voltage-controlled oscillators (VCOs). The VCOs are discrete components based on surface acoustic wave (SAW) or high frequency fundamental (HFF) inverted mesa crystal resonators. Since these devices are only capable of operating within a few hundred parts per million (ppm) of a center frequency, multi-protocol support requires many different VCOs. The overall system implications include increased cost, board space, bill-of-materials (BOM) and supply issues. In addition, these crystal and SAW-based oscillators introduce various reliability issues including temperature drift and long-term aging. While the frequency control industry has made some progress supporting dual frequency applications by packaging multiple resonators in a single module package, this approach is difficult to scale past two frequencies, and it does not address the inherent frequency instabilities of high frequency SAW and HFF resonators.Today, advancements in fine-line CMOS technology have increased speed and computing power, making possible a DSP-based clock IC that enables a new class of high frequency, low jitter voltage-controlled crystal oscillators (VCXOs). This new approach combines a DSP clock IC together with a fixed, low frequency crystal resonator to realize the functional equivalent of a traditional high frequency VCO but with a user programmable frequency range from 10MHz to well over 1GHz. Jitter performance is comparable to the best SAW and HFF narrowband oscillators but frequency agility provides coverage for multiple services and the associated FEC frequencies with one device. In addition, the DSP IC at the core of the VCXO moves many functions into the digital domain enabling new features like programmable pull range and VCO gain with very high resolution. Finally, VCXOs using this new DSP clock technology exhibit superior aging and temperature stability characteristics when compared to tradition high frequency SAW or HFF-based VCO devices.In summary, a new class of frequency agile VCXO devices is now possible that will radically alter the timing system architecture of multi-service systems while improving overall performance and reliability. In these systems, multiple parallel PLL circuits based on fixed frequency SAW or HFF crystals can be replaced by one frequency agile VCXO based on a DSP clock IC technology. This technology promises to deliver significant improvements in cost, board space, reliability and supply chain management.
© 2006 Optical Society of AmericaPDF Article