This paper presents an overview of the work done by Hewlett Packard Labs to enable a high bandwidth, scalable and cost-effective interconnect solution. This fabric is demanded by the high-performance computing and data center architectures proposed to solve tomorrow’s Big Data and Machine Learning problems. We outline the proposed link architecture, review the various components that enable this link and discuss the co-packaged form factor for dense, high-performance integration with large radix switches and compute components.

© 2019 The Author(s)

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