Transfer rates in optical transmission systems are usually higher than the clocking speed of silicon devices. Thus parallelization has to be introduced, which means that several samples have to be processed during one operating cycle. For such a parallelized receiver structure a feedforward timing recovery scheme is implemented into an FPGA.

© 2012 Optical Society of America

PDF Article
More Like This
Structure of a Digital Feedback Clock Recovery for Parallelized Receivers

Daniel Schmidt and Berthold Lankl
SPTuC2 Signal Processing in Photonic Communications (SPPCom) 2011

Real-time implementation of parallel digital timing recovery algorithm with reduced complexity

Ruibin Hao, Yan Li, Xiaodong Wang, Jian Wu, Jifang Qiu, and Xiaobin Hong
Su3D.4 Asia Communications and Photonics Conference (ACPC) 2018

Implementation of Coherent 16-QAM Digital Receiver With Feedforward Carrier Recovery

A. Al-Bermani, C. Wördehoff, S. Hoffmann, T. Pfau, U. Rückert, and R. Noé
SPWB5 Signal Processing in Photonic Communications (SPPCom) 2010


You do not have subscription access to this journal. Citation lists with outbound citation links are available to subscribers only. You may subscribe either as an Optica member, or as an authorized user of your institution.

Contact your librarian or system administrator
Login to access Optica Member Subscription