This paper describes an optical interconnect solution based on a monolithic photonic CMOS architecture. A photonic CMOS process enables higher bandwidth and lower energy-per-bit for chip-to-chip optical I/O through integration of electro-optical polymer based modulators, silicon nitride waveguides and polycrystalline germanium (Ge) photodetectors in a CMOS logic process. Experimental results for both the photonic CMOS ring resonator modulators and Ge detectors demonstrate 40 Gb/s performance.

© 2010 Optical Society of America

PDF Article
More Like This
Optical I/O for Chip-to-Chip Interconnects on CMOS Platform

Peter L.D. Chang, Edris M. Mohammed, Bruce A. Block, Miriam R. Reshotko, and Ian A. Young
OThQ1 Optical Fiber Communication Conference (OFC) 2011

Silicon-Photonics Devices for Low-Power, High-Bandwidth Optical I/O

J. Van Campenhout, M. Pantouvaki, P. Verheyen, H. Yu, P. De Heyn, G. Lepage, W. Bogaerts, and P. Absil
ITu2B.1 Integrated Photonics Research, Silicon and Nanophotonics (IPRSN) 2012

Device Requirements for Optical Interconnects to CMOS Silicon Chips

David A. B. Miller
PMB3 Photonics in Switching (PS) 2010


You do not have subscription access to this journal. Citation lists with outbound citation links are available to subscribers only. You may subscribe either as an Optica member, or as an authorized user of your institution.

Contact your librarian or system administrator
Login to access Optica Member Subscription