Expand this Topic clickable element to expand a topic
Skip to content
Optica Publishing Group
Conferences > ACPC > 2021 > T4A > T4A.67

An Improved FPGA Equivalent Parallel Implementation of All-digital Timing Recovery

Xun Lu, Liqian Wang, Yuhua Wang, and Xue Chen

Not Accessible

Your library or personal account may give you access

Abstract

In the all-digital timing recovery algorithm based on FPGA, an improved equivalent parallel implementation is proposed. It solves the problem that numerically controlled oscillator cannot updata in real time. Its is verified in PM-QPSK system.

© 2021 The Author(s)

PDF Article
More Like This
Real-time implementation of parallel digital timing recovery algorithm with reduced complexity

Ruibin Hao, Yan Li, Xiaodong Wang, Jian Wu, Jifang Qiu, and Xiaobin Hong
Su3D.4 Asia Communications and Photonics Conference (ACP) 2018

Real-Time FPGA Demonstration of PAM-4 Burst-Mode All-Digital Clock and Data Recovery for Single wavelength 50G PON Application

Junwen Zhang, Xin Xiao, Jianjun Yu, Jun Shan Wey, Xingang Huang, and Zhuang Ma
M1B.7 Optical Fiber Communication Conference (OFC) 2018

FPGA Implementation of Carrier Recovery Algorithm for QPSK Coherent Optical Communication Systems

Jian Yang, Zhixiang Luo, Sheng Cui, Changjian Ke, and Deming Liu
AF4F.3 Asia Communications and Photonics Conference (ACP) 2016

View More...
Select as filters
Select Topics Cancel
Top
       
© Copyright 2024 | Optica Publishing Group. All rights reserved, including rights for text and data mining and training of artificial technologies or similar technologies.
Privacy | Terms of Use