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Conferences > ACPC > 2012 > AF3C > AF3C.2

FPGA Implementaion of FEC for 10G-EPON

Xicong Li, Yinying Cao, Xue Chen, and Weidong Gao

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Abstract

New parallel RS(255,223) encoder and decoder architectures for 10G EPON FEC are presented and realized in FPGA. The proposed architectures can operate at 156.25MHz to achieve the throughput of 10.3125Gbps with small hardware-complexity and low latency.

© 2012 Optical Society of America

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