Abstract

We use a 65nm CMOS process technology to develop 40Gbit/s interface conversion prototype circuits for 40GbE, STM-256/OC-768 and OTU3 tri-rate serial signal transport. For the first time, interface conversion functions from SFI-5.1 to SFI-5.2/XLAUI are demonstrated on a 16:4 MUX prototype chip, and from SFI-5.2/XLAUI to SFI-5.1 on a 4:16 DEMUX prototype chip. The 16:4 MUX and 4:16 DEMUX prototype chips show excellent jitter performance and consume 1.6 and 1.7 W, respectively.

© 2010 Optical Society of America