The state-of-the-art of on-chip tunable delay lines in silicon-on-insulator technology is discussed. Architectures, theoretical results, limits and experimental results up to 10 bits delay at 100 Gbit/s are presented.

© 2010 Optical Society of America

PDF Article


You do not have subscription access to this journal. Citation lists with outbound citation links are available to subscribers only. You may subscribe either as an OSA member, or as an authorized user of your institution.

Contact your librarian or system administrator
Login to access OSA Member Subscription